Advance Information
CAT24C208
FEATURES
s
400 kHz I
2
C bus compatible*
s
Complies with VESA E-EDID, E-DDC, DI-EXT
8K (1K x 8) -Bit Dual Port Serial EEPROM for VESA Plug and Play Applications
LE
in LCD Projectors and Monitors
A
D
F
R
E
E
TM
s
1,000,000 program/erase cycles
s
100 year data retention
s
8-pin DIP, SOIC, TSSOP or MSOP packages
and M1 specifications
s
1.8 to 5.5 volt operation
s
Low power CMOS technology
s
16-byte page write buffer
s
Self-timed write cycle with auto-clear
- Green package option
s
Industrial and extended temperature ranges
DESCRIPTION
The CAT24C208 is an 8k-bit Dual Port Serial CMOS
EEPROM internally organized as 1k words of 8 bits
each. The CAT24C208 features a 16-byte page write
buffer and can be accessed from either of two separate
I2C compatible ports, DSP (SDA, SCL) and DDC (SDA,
SCL) which conform to the VESA E-EDID EEPROM
Standard.
Arbitration between the two interface ports is automatic
and allows the appearance of simultaneous access to
the memory from both interfaces.
Using Catalyst's advanced CMOS technology which
substantially reduces device power requirements, the
CAT24C208 can be powered from either of two
independent V
CC
inputs.
The CAT24C208 operates over the full industrial and
extended temperature range and is available in
miniature 8-pin DIP, SOIC, TSSOP and MSOP
packages.
BLOCK DIAGRAM
DSP VCC
ARBITRATION
LOGIC
DDC VCC
DSP SCL
DSP SDA
DISPLAY
CONTROL
LOGIC
D
E
C
O
D
E
R
S
1K X 8
MEMORY
ARRAY
D
E
C
O
D
E
R
S
DDC
CONTROL
LOGIC
DDC SCL
DDC SDA
VSS
CONFIGURATION
REGISTER
DDC SEL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1044, Rev. B
1
H
GEN
FR
ALO
EE
CAT24C208
PIN CONFIGURATION
DIP Package (P, L)
DSP VCC
DSP SCL
DSP SDA
VSS
1
2
3
4
8
7
6
5
DDC VCC
EDID SEL
DDC SCL
DDC SDA
SOIC Package (J, W)
DSP VCC
DSP SCL
DSP SDA
VSS
1
2
3
4
8
7
6
5
DDC VCC
EDID SEL
DDC SCL
DDC SDA
MSOP Package (R, Z)
DSP VCC
DSP SCL
DSP SDA
VSS
1
2
3
4
8
7
6
5
DDC VCC
EDID SEL
DDC SCL
DDC SDA
DSP VCC
DSP SCL
DSP SDA
VSS
TSSOP Package (U, Y)
1
2
3
4
8
7
6
5
DDC VCC
EDID SEL
DDC SCL
DDC SDA
PIN DESCRIPTION
Pin Number
1
2
Pin Name
DSP V
CC
DSP SCL
Function
Device power from display controller
The CAT24C208 DSP serial clock input pin is used to clock all data
transfers into or out of the device DSP SDA pin.
DSP Serial Data/Address. The bidirectional DSP serial
data/address pin is used to transfer data into and out of the device
from a display controller. The DSP SDA pin is an open drain output
and can be wire-OR'ed with other open drain or open collector
outputs.
Device ground.
DDC Serial Data/Address. The bidirectional DDC serial
data/address pin is used to transfer data into and out of the device
from a DDC host. The DDC SDA pin is an open drain output and
can be wire-OR'ed with other open drain or open collector outputs.
The CAT24C208 DDC serial clock input pin is used to clock all data
transfers into or out of the device DDC SDA pin.
EDID select. The CAT24C208 EDID select input selects the active
bank of memory to be accessed via the DDC SDA/SCL interface as
set in the configuration register.
Device power when powered from a DDC host.
3
DSP SDA
4
V
SS
5
DDC SDA
6
DDC SCL
7
8
EDID SEL
DDC V
CC
Doc. No. 1044, Rev. B
2
CAT24C208
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
............ -2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Reference Test Method
Min
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
MIL-STD-883, Test Method 1033 1,000,000
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
4000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
VHYS
V
OL1
V
OL2
V
CCL1
V
CCL2
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Hysteresis
Output Low Voltage (V
CC
= 3.0V)
Output Low Voltage (V
CC
= 1.8V)
Leakage DSP to V
CC
DDC to V
CC
Leakage DDC V
CC
to DSP V
CC
Test Conditions
f
SCL
= 100 KHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
Min
Typ
Max
3
0
10
10
Units
mA
µA
µA
µA
V
V
V
–1
V
CC
x 0.7
0.05
I
OL
= 3 mA
I
OL
= 1.5 mA
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
100
100
V
V
µA
µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Standby Current (I
SB
) = 0µA (<900nA).
3
Doc. No. 1044, Rev. B
CAT24C208
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (VCLK, SCL)
Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8V-5.5V
Min
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
4
100
4.7
4
4.7
4
4.7
0
50
1
300
0.6
100
Max
100
200
3.5
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
2.5V-5.5V
Min
Max
400
200
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Doc. No. 1044, Rev. B
4
CAT24C208
Write Cycle Limits
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
FUNCTIONAL DESCRIPTION
The CAT24C208 has a total memory space of 1K bytes
which is accessible from either of two I
2
C interface ports,
(DSP_SDA and DSP_SCL) or (DDC_SDA and
DDC_SCL).
The entire memory appears as contiguous memory
space from the perspective of the display interface
(DSP_SDA and DSP_SCL).
A configuration register at addresses 62/63h is used to
configure the operation and memory map of the device
as seen from the DDC interface, (DDC_SDA and
DDC_SCL).
Read and write operations can be performed on any
location within the memory space from the display
interface regardless of the state of the EDID SEL pin or
the activity on the DDC interface. From the DDC
interface, the memory space appears as either one large
1K byte bank of memory or as two 500 byte banks of
memory.
Each bank of memory can be used to store an E-EDID
data structure. However, only one bank can be read
through the DDC port at a time. The active bank of
memory (that is, the bank that appears at address A0h
on the DDC port) is controlled through the configuration
register at 62h and the EDID_SEL pin.
No write operations are possible from the DDC interface
unless the DDC Write Enable bit is set (WE = 1) in the
device configuration register at device address 62h.
The device automatically arbitrates between the two
interfaces to allow the appearance of simultaneous
access to the memory from both interfaces.
In a typical E-EDID application the EDID_SEL pin is
usually connected to the “Analog Cable Detect” pin of a
VESA M1 compliant, dual-mode (analog and digital)
display. In this manner, the E-EDID appearing at ad-
dress A0h on the DDC port will be either the analog or
digital E-EDID, depending on the state of the “Analog
Cable Detect” pin (pin C3 of the M1-DA connector). See
Figure 1.
Figure 1.
M1-DA CONNECTOR
28
DDC +5V
+5VDC
(SUPPLIED
BY DISLAY)
10K
47.5K
C3
27
28
DDC CLK
8
7
6
5
E-EDID
EEPROM
1
2
3
4
I2C TO PROJECTOR/MONITOR
DISPLAY CONTROLLER
TO HOST
CONTROLLER
DDC DATA
FUSE, RESISTOR
OR OTHER
CURRENT LIMITING
DEVICE REQUIRED
IN ALL M1 DISPLAYS
26
HPD
2A MAX
RELAY CONTACTS SHOWN IN
DE-ENERGIZED POSITION
5
Doc. No. 1044, Rev. B
微控制器 MCU
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