Integrated Device Technology, Inc.
BiCMOS StaticRAM
240K (16K x 15-BIT)
CACHE-TAG RAM
For PowerPC
™
and RISC Processors
IDT71216
FEATURES:
• 16K x 15 Configuration
– 12 TAG Bits
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
• Match output uses Valid bit to qualify MATCH output
• High-Speed Address-to-Match comparison times
– 8/9/10/12ns over commercial temperature range
•
TA
circuitry included inside the Cache-Tag for highest
speed operation
• Asynchronous Read/Match operation with Synchronous
Write and Reset operation
• Separate
WE
for the TAG bits and the Status bits
• Separate
OE
for the TAG bits, the Status bits, and
TA
• Synchronous
RESET
pin for invalidation of all Tag entries
• Dual Chip selects for easy depth expansion with no
performance degredation
• I/O pins both 5V TTL and 3.3V LVTTL compatible with
V
CCQ
pins
•
PWRDN
pin to place device in low-power mode
• Packaged in a 80-pin Thin Plastic Quad Flat Pack
(TQFP)
DESCRIPTION:
The IDT71216 is a 245,760-bit Cache Tag StaticRAM,
organized 16K x 15 and designed to support PowerPC and
other RISC processors at bus speeds up to 66MHz. There are
twelve common I/O TAG bits, with the remaining three bits
used as status bits. A 12-bit comparator is on-chip to allow fast
comparison of the twelve stored TAG bits and the current Tag
input data. An active HIGH MATCH output is generated when
these two groups of data are the same for a given address.
This high-speed MATCH signal, with t
ADM
as fast as 8ns,
provides the fastest possible enabling of secondary cache
accesses.
The three separate I/O status bits (VLD, DTY, and WT) can
be configured for either dedicated or generic functionality,
depending on the SFUNC input pin. With SFUNC LOW, the
status bits are defined and used internally by the device,
allowing easier determination of the validity and use of the
given Tag data. SFUNC HIGH releases the defined internal
status bit usage and control, allowing the user to configure the
status bit information to fit his system needs. A synchronous
RESET
pin, when held LOW at a rising clock edge, will reset
all status bits in the array for easy invalidation of all Tag
addresses.
The IDT71216 also provides the option for Transfer Ac-
knowledge (
TA
) generation within the cache tag itself, based
upon MATCH, VLD bit, WT bit, and external inputs provided
by the user. This can significantly simplify cache controller
logic and minimize cache decision time. Match and Read
operations are both asynchronous in order to provide the
fastest access times possible, while Write operations are
synchronous for ease of system timing.
The IDT71216 uses a 5V power supply on Vcc, with
separate V
CCQ
pins provided for the outputs to offer compli-
ance with both 5.0V TTL and 3.3V LVTTL Logic levels. The
PWRDN
pin offers a low-power standby mode to reduce
power consumption by 90%, providing significant system
power savings.
The IDT71216 is fabricated using IDT's high-performance,
high-reliability BiCMOS technology and is offered in a space-
saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.
PIN DESCRIPTIONS
A
0
– A
13
Address Inputs
Chip Selects
Write Enable - Tag Bits
Write Enable - Status Bits
Output Enable - Tag Bits
Output Enable - Status Bits
Status Bit Reset
Powerdown Mode Control Pin
Status Bit Function Control Pin
Read/Write Input from Processor
Valid Bit / S
1
Bit Input
Dirty Bit / S
2
Bit Input
Write Through Bit / S
3
Bit Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
CLK
TAH
System Clock
Input
Input
Input
Input
Output
I/O
Output
Output
Output
Output
Pwr
QPwr
Gnd
3067 tbl 01
The IDT logo is a registered trademark and CacheRAM is a trademark of Integrated Device Technology, Inc.
PowerPC is a trademark of International Business Machines, Inc.
CS1
, CS2
WET
WES
OET
OES
RESET
PWRDN
SFUNC
TT1
VLD
IN
/ S
1IN
DTY
IN
/ S
2IN
WT
IN
/ S
3IN
TAOE
TAIN
TA
TAG
0
– TAG
11
VLD
OUT
/ S
1OUT
DTY
OUT
/ S
2OUT
WT
OUT
/ S
3OUT
MATCH
V
CC
V
CCQ
V
SS
TA
Force High
TA
Output Enable
Additional
TA
Input
Transfer Acknowledge
Tag Data Input/Outputs
Valid Bit / S
1
Bit Output
Dirty Bit / S
2
Bit Output
Write Through Bit / S
3
Bit Output
Match
+5V Power
Output Buffer Power
Ground
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-3067/3
14.3
1
IDT71216
BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLES (CONT.)
MATCH FUNCTION
(1, 2, 3)
CS1
CS2 SFUNC
OET WET WES
H
X
L
L
L
L
L
L
L
X
L
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
H
X
X
X
L
H
X
H
H
H
X
X
X
H
L
X
H
H
H
X
X
X
X
X
L
H
H
H
TAG
Hi-Z
Hi-Z
–
D
OUT
D
IN
–
TAG
IN
TAG
IN
TAG
IN
VLD
(4)
DTY
(4)
WT
(4)
MATCH
–
–
–
–
–
D
IN
L
H
X
–
–
–
–
–
D
IN
–
–
–
–
–
–
–
–
D
IN
–
–
–
Hi-Z
Hi-Z
D
OUT
L
L
L
L
M
M
OPERATION
Deselected
Deselected
Selected
Read Tag I/O
Write Tag I/O
Write Status Bits
Invalid Data - Dedicated Status Bits
Match - Dedicated Status Bits
Match - Generic Status Bits
3067 tbl 04
NOTES:
1. "H" = V
IH
, "L" = V
IL
, "X" = don't care, "–" = unrelated.
2. M = HIGH if TAG
IN
equals the memory contents at that address; M = LOW if TAG
IN
does not equal the memory contents at that address.
3.
PWRDN
and
RESET
are HIGH for this table. TT1, TAH,
TAOE
,
TAIN
,
OES
, and CLK are "X".
4. This column represents the stored memory cell data for the given Status bit at the selected address.
TA
FUNCTION
(1, 2, 3, 5)
TAOE
H
L
L
L
L
L
L
L
L
L
L
L
TAIN
(6)
OET WET WES
X
L
H
H
H
H
H
H
H
H
H
H
X
X
L
X
X
X
X
X
H
H
H
H
X
X
X
L
X
X
X
X
H
H
H
H
X
X
X
X
L
X
X
X
H
H
H
H
TAH
X
X
X
X
X
H
X
X
L
L
L
L
TT1 SFUNC
X
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
X
X
L
L
L
L
L
H
VLD
(4)
DTY
(4)
WT
(4)
TAG MATCH
X
X
X
X
D
IN
X
L
X
H
H
H
X
–
–
–
–
D
IN
–
–
–
–
–
–
–
X
X
X
X
D
IN
X
X
H
L
X
X
X
–
–
D
OUT
D
IN
–
–
–
–
TAG
IN
TAG
IN
TAG
IN
TAG
IN
–
X
L
L
L
X
L
X
M
M
M
M
TA
Hi-Z
L
H
H
H
H
H
H
OPERATION
TA
Disabled
External
TA
Input
(7)
Read TAG
Write TAG
Write Status
Force
TA
HIGH
Invalid TAG
Write Through
Compare
Compare
Compare
Compare
M
M
M
M
NOTES:
3067 tbl 05
1. "H" = V
IH
, "L" = V
IL
, "X" = don't care, "–" = unrelated.
2. M = HIGH if TAG
IN
equals the memory contents at that address; M = LOW if TAG
IN
does not equal the memory contents at that address.
3.
PWRDN
and
RESET
are HIGH for this table. CLK and
OES
are "X".
4. This column represents the stored memory cell data for the given Status bit at the selected address.
5.
CS1
is LOW, CS2 is HIGH for this table.
6.
TAIN
is a synchronous input; thus the inputs noted in the table must be applied during a rising CLK edge.
7.
TAIN
will be a factor in determining the
TA
output in all cases except when TAH is HIGH and there is a valid MATCH. In that case,
TA
will be LOW(Valid).
14.3
5
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