CMOS STATIC RAM
1 MEG (256K x 4-BIT)
Integrated Device Technology, Inc.
IDT71028
FEATURES:
• 256K x 4 advanced high-speed CMOS static RAM
• Equal access and cycle times
— Commercial: 12/15/17/20ns
• One Chip Select plus one Output Enable pin
• Bidirectional data Inputs and outputs directly
TTL-compatible
• Low power consumption via chip deselect
• Available in 400 mil Plastic SOJ package
DESCRIPTION:
The IDT71028 is a 1,048,576-bit high-speed static RAM
organized as 256K x 4. It is fabricated using IDT’s high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71028 has an output enable pin which operates as
fast as 6ns, with address access times as fast as 12ns. All
bidirectional inputs and outputs of the IDT71028 are TTL-
compatible and operation is from a single 5V supply. Fully
static asynchronous circuitry is used, requiring no clocks or
refresh for operation.
The IDT71028 is packaged in 28-pin 400 mil Plastic SOJ
package.
FUNCTIONAL BLOCK DIAGRAM
A
0
ADDRESS
DECODER
1,048,576-BIT
MEMORY
ARRAY
A
17
I/O
0
– I/O
3
4
4
I/O CONTROL
CS
WE
OE
CONTROL
LOGIC
2966 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
AUGUST 1996
9.4
DSC-2966/5
1
IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
CS
OE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Com’l.
–0.5 to +7.0
Unit
V
GND
1
28
27
2
3
26
25
4
24
5
23
6
SO28-6
22
7
21
8
9
20
10
19
11
18
17
12
13
16
15
14
SOJ
TOP VIEW
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
V
TERM
(2)
T
A
T
BIAS
T
STG
P
T
I
OUT
0 to +70
–55 to +125
–55 to +125
1.25
50
°C
°C
°C
W
mA
2966 drw 02
NOTES:
2966 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
TRUTH TABLE
(1,2)
CS
OE
WE
CAPACITANCE
I/O
Function
Read Data
Write Data
Output Disabled
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB1
)
2966 tbl 01
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
8
8
Unit
pF
pF
L
L
L
H
V
HC
(3)
L
X
H
X
X
H
L
H
X
X
DATA
OUT
DATA
IN
High-Z
High-Z
High-Z
NOTE:
2966 tbl 03
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
-0.2V.
3. Other inputs
≥V
HC
or
≤V
LC
.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max.
5.5
0
V
CC
+0.5
0.8
Unit
V
V
V
V
NOTE:
2966 tbl 04
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%
IDT71028
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= –4mA, V
CC
= Min.
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
2966 tbl 05
9.4
2
IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5.0V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
– 0.2V)
71028S12
(3)
Symbol
I
CC
Parameter
Dynamic Operating Current,
CS
≤
V
IL
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current
(TTL Level),
CS
≥
V
IH
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
Full Standby Power Supply Current
(CMOS Level),
CS
≥
V
HC
, Outputs Open,
V
CC
= Max., f = 0
(2)
, V
IN
≤
V
LC
or V
IN
≥
V
HC
155
—
71028S15
150
—
71028S17
145
—
71028S20
Com'l. Mil.
145
—
Unit
mA
Com'l. Mil. Com'l. Mil. Com'l. Mil.
I
SB
35
—
35
—
35
—
35
—
mA
I
SB1
10
—
10
—
10
—
10
—
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
3. 12ns specification is preliminary.
2966 tbl 06
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
2966 tbl 07
5V
480
Ω
DATA
OUT
30pF
255
Ω
2966 drw 03
5V
480
Ω
DATA
OUT
5pF*
255
Ω
2966 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
9.4
3
IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, Commercial Temperature Range)
Symbol
Parameter
71028S12
(1)
71028S15 71028S17
71028S20
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ(2)
t
CHZ(2)
t
OE
t
OLZ(2)
t
OHZ(2)
t
OH
t
PU(2)
t
PD(2)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
12
—
—
3
0
—
0
0
4
0
—
—
12
12
—
6
6
—
5
—
—
12
15
—
—
3
0
—
0
0
4
0
—
—
15
15
—
7
7
—
5
—
—
15
17
—
—
3
0
—
0
0
4
0
—
—
17
17
—
8
8
—
6
—
—
17
20
—
—
3
0
—
0
0
4
0
—
—
20
20
—
8
8
—
7
—
—
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW(2)
t
WHZ(2)
Write Cycle Time
Address Valid to End of Write
Chip Select to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Output Active from End of Write
Write Enable to Output in High-Z
12
10
10
0
10
0
7
0
3
0
—
—
—
—
—
—
—
—
—
5
15
12
12
0
12
0
8
0
3
0
—
—
—
—
—
—
—
—
—
5
17
13
13
0
13
0
9
0
3
0
—
—
—
—
—
—
—
—
—
7
20
15
15
0
15
0
9
0
4
0
—
—
—
—
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2966 tbl 08
NOTES:
1. 12ns specification is preliminary.
2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
9.4
4
IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
OLZ (5)
(5)
t
ACS
(3)
t
CLZ
DATA
OUT
t
CHZ (5)
t
OHZ (5)
HIGH IMPEDANCE
DATA
OUT
VALID
t
PD
V
CC
SUPPLY I
CC
CURRENT I
SB
t
PU
2966 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
2966 drw 6
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured
±200mV
from steady state.
9.4
5
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