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IDT70T651S15BC: 产品描述Dual-Port SRAM, 256KX36, 15ns, CMOS, PBGA256, BGA-256; 产品类别存储存储; 文件大小339KB，共27页; 制造商IDT (Integrated Device Technology)

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IDT70T651S15BC概述

Dual-Port SRAM, 256KX36, 15ns, CMOS, PBGA256, BGA-256

IDT70T651S15BC规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	BGA
包装说明	LBGA, BGA256,16X16,40
针数	256
Reach Compliance Code	not_compliant
ECCN代码	3A991.B.2.A
最长访问时间	15 ns
I/O 类型	COMMON
JESD-30 代码	S-PBGA-B256
JESD-609代码	e0
长度	17 mm
内存密度	9437184 bit
内存集成电路类型	DUAL-PORT SRAM
内存宽度	36
湿度敏感等级	3
功能数量	1
端口数量	2
端子数量	256
字数	262144 words
字数代码	256000
工作模式	ASYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	256KX36
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装等效代码	BGA256,16X16,40
封装形状	SQUARE
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	225
电源	2.5,2.5/3.3 V
认证状态	Not Qualified
座面最大高度	1.5 mm
最大待机电流	0.01 A
最小待机电流	2.4 V
最大压摆率	0.305 mA
最大供电电压 (Vsup)	2.6 V
最小供电电压 (Vsup)	2.4 V
标称供电电压 (Vsup)	2.5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn63Pb37)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	20
宽度	17 mm

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Features

◆

HIGH-SPEED 2.5V

256/128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

PRELIMINARY

IDT70T651/9S

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 8/10/12/15ns (max.)

– Industrial: 10/12ns (max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T651/9 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

◆

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad

Flatpack and 208-ball fine pitch Ball Grid Array.

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Functional Block Diagram

BBBB

EEEE

3210

R RRR

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_L Dout18-26_R

Dout27-35_L Dout27-35_R

256/128K x 36

MEMORY

ARRAY

I/O

0L-

I/O

35L

Di n_L

Di n_R

I/O

0R -

I/O

35R

17L(1)

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

17R(1)

R/W

BUSY

L (2,3)

SEM

INT

L(3)

(4)

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

TDI

TD O

JTAG

TC K

TMS

TRST

M/S

BUSY

R(2,3)

SEM

INT

R(3)

(4)

NOTES:

1. Address A

17x

is a NC for IDT70T659.

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,

INTx,

M/S and the sleep

mode pins themselves (ZZx) are not affected during sleep mode.

CONTROL

LOGIC

4869 drw 01

NOVEMBER 2003

DSC-5632/3

IDT70T651S15BC

IDT70T651S15BC概述

IDT70T651S15BC规格参数

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