The IDT70T3509M is a high-speed 1024K x 36 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times. With an input data register, the
IDT70T3509M has been optimized for applications having unidirectional
or bidirectional data flow in bursts. An automatic power down feature,
controlled by
CE
0
and CE
1,
permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70T3509M can support an operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (V
DD
) is at 2.5V.
6.42
2
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Pin Configuration
(1,2,3,4)
70T3509M BP
BP-256
(5,7)
256-Pin BGA
Top View
(6)
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
08/03/04
A1
NC
B1
TDI
B2
A
19L
B3
A
17L
B4
A
14L
B5
A
11L
B6
A
8L
B7
BE
2L
B8
CE
1L
B9
OE
L
CNTEN
L
A
5L
B10
B11
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
I/O
18L
C1
NC
C2
TDO
C3
A
18L
C4
A
15L
C5
A
12L
C6
A
9L
C7
BE
3L
C8
CE
0L
R/W
L
REPEAT
L
C9
C10
C11
A
4L
C12
A
1L
C13
V
DD
C14
I/O
17L
C15
NC
C16
I/O
18R
I/O
19L
D1
D2
V
SS
D3
A
16L
D4
A
13L
D5
A
10L
D6
A
7L
D7
BE
1L
D8
BE
0L
CLK
L
ADS
L
D9
D10
D11
A
6L
D12
A
3L
D13
OPT
L
I/O
17R
I/O
16L
D14
D15
D16
I/O
20R
I/O
19R
I/O
20L
PIPE/
FT
L
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
I/O
15R
I/O
15L
I/O
16R
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
I/O
21R
I/O
21L
I/O
22L
V
DDQL
F1
F2
F3
F4
V
DD
F5
V
DD
F6
INT
L
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
I/O
13L
I/O
14L
I/O
14R
F12
F13
F14
F15
F16
I/O
23L
I/O
22R
I/O
23R
V
DDQL
V
DD
G1
G2
G3
G4
G5
NC
G6
NC
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
V
DDQR
I/O
12R
I/O
13R
I/O
12L
G12
G13
G14
G15
G16
I/O
24R
I/O
24L
I/O
25L
V
DDQR
H1
H2
H3
H4
V
SS
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
I/O
10L
I/O
11L
I/O
11R
H13
H14
H15
H16
I/O
26L
I/O
25R
I/O
26R
V
DDQR
V
SS
J1
J2
J3
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
I/O
9R
J13
J14
IO
9L
I/O
10R
J15
J16
I/O
27L
I/O
28R
I/O
27R
V
DDQL
K1
K2
K3
K4
ZZ
R
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
ZZ
L
K12
V
DDQR
I/O
8R
I/O
7R
K13
K14
K15
I/O
8L
K16
I/O
29R
I/O
29L
I/O
28L
V
DDQL
L1
L2
L3
L4
V
SS
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
I/O
6R
I/O
6L
I/O
7L
L13
L14
L15
L16
I/O
30L
I/O
31R
I/O
30R
V
DDQR
V
DD
M1
M2
M3
M4
M5
NC
M6
NC
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
5L
M13
M14
I/O
4R
I/O
5R
M15
M16
I/O
32R
I/O
32L
I/O
31L
V
DDQR
N1
N2
N3
N4
V
DD
N5
V
DD
N6
INT
R
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
N12
V
DDQL
I/O
3R
N13
N14
I/O
3L
I/O
4L
N15
N16
I/O
33L
I/O
34R
I/O
33R
P IP E /
FT
R
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
V
DD
P13
I/O
2L
P14
I/O
1R
I/O
2R
P15
P16
I/O
35R
I/O
34L
TMS
R1
R2
R3
A
16R
R4
A
13R
R5
A
10R
R6
A
7R
R7
BE
1R
BE
0R
CLK
R
ADS
R
R8
R9
R10
R11
A
6R
R12
A
3R
R13
I/O
0L
I/O
0R
R14
R15
I/O
1L
R16
I/O
35L
T1
NC
T2
TRST
A
18R
T3
T4
A
15R
T5
A
12R
T6
A
9R
T7
BE
3R
CE
0R
R/W
R
REPEAT
R
A
4R
T8
T9
T10
T11
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
,
NC
TCK
A
19R
A
17R
A
14R
A
11R
A
8R
BE
2R
CE
1R
OE
R
CNTEN
R
A
5R
A
2R
A
0R
NC
NC
5682 drw 02d
NOTES:
,
1. All V
DD
pins must be connected to 2.5V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
DD
(2.5V), and 2.5V if OPT pin for that port is
set to V
SS
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.76mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. BP-256 package thickness is 1.76mm nominal. This is thicker than the BC-256 package (1.40mm nominal) used for the lower density IDT dual-port products.
6.42
3
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
19L
I/O
0L
- I/O
35L
CLK
L
PL/FT
L
ADS
L
CNTEN
L
REPEAT
L
BE
0L
-
BE
3L
V
DDQL
OPT
L
ZZ
L
V
DD
V
SS
TDI
TDO
TCK
TMS
TRST
INT
L
INT
R
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
19R
I/O
0R
- I/O
35R
CLK
R
PL/FT
R
ADS
R
CNTEN
R
REPEAT
R
BE
0R
-
BE
3R
V
DDQR
OPT
R
ZZ
R
Names
Chip Enables (Input)
(5)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat
(3)
(Input)
Byte Enables (9-bit bytes) (Input)
(5)
Power (I/O Bus) (3.3V or 2.5V)
(1)
(Input)
Option for selecting V
DDQX
(1,2)
(Input)
Sleep Mode pin
(4)
(Input)
Power (2.5V)
(1)
(Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
5682 tbl 01
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to V
DD
(2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to V
SS
(0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX
must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundary scan not be operated during sleep mode.
5. Chip Enables and Byte Enables are double buffered when PL/FT = V
IH
, i.e., the
signals take two cycles to deselect.
6.42
4
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Truth Table I—Read/Write and Enable Control
OE
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
X
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE
0
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
CE
1
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
BE
3
X
X
X
H
H
H
H
L
H
L
L
H
H
H
L
H
L
L
X
X
BE
2
X
X
X
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
X
X
BE
1
X
X
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
X
X
BE
0
X
X
X
H
L
H
H
H
L
H
L
L
H
H
H
L
H
L
X
X
R/W
X
X
X
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
X
X
ZZ
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Byte 3
I/O
27-35
High-Z
Active
Active
High-Z
High-Z
High-Z
High-Z
D
IN
High-Z
D
IN
D
IN
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
OUT
High-Z
High-Z
Byte 2
I/O
18-26
High-Z
Active
Active
High-Z
High-Z
High-Z
D
IN
High-Z
High-Z
D
IN
D
IN
High-Z
High-Z
D
OUT
High-Z
High-Z
D
OUT
D
OUT
High-Z
High-Z
(1,2,3,4)
Byte 1
I/O
9-17
High-Z
Active
Active
High-Z
High-Z
D
IN
High-Z
High-Z
D
IN
High-Z
D
IN
High-Z
D
OUT
High-Z
High-Z
D
OUT
High-Z
D
OUT
High-Z
High-Z
Byte 0
I/O
0-8
High-Z
Active
Active
High-Z
D
IN
High-Z
High-Z
High-Z
D
IN
High-Z
D
IN
D
OUT
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
High-Z
High-Z
MODE
Deselected–Power Down
Not Allowed
Not Allowed
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
Read Byte 0 Only
Read Byte 1 Only
Read Byte 2 Only
Read Byte 3 Only
Read Lower 2 Bytes Only
Read Upper 2 Bytes Only
Read All Bytes
Outputs Disabled
Sleep Mode
5682 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, REPEAT
= V
IH
.
3.
OE
and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
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