HIGH-SPEED
64K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
x
IDT707288S/L
Features
64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
– Four independent 16K x 16 banks
– 1 Megabit of memory on chip
Fast asynchronous address-to-data access time: 15ns
User-controlled input pins included for bank selects
Independent port controls with asynchronous address &
data busses
Four 16-bit mailboxes available to each port for inter-
x
x
x
x
x
x
x
x
processor communications; interrupt option
Interrupt flags with programmable masking
Dual Chip Enables allow for depth expansion without
external logic
UB
and
LB
are available for x8 or x16 bus matching
TTL-compatible, single 5V (±10%) power supply
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)
x
Functional Block Diagram
MUX
R/W
L
CE
0L
CE
1L
UB
L
LB
L
OE
L
16Kx16
MEMORY
ARRAY
(BANK 0)
MUX
I/O
8L-15L
I/O
0L-7L
I/O
CONTROL
MUX
16Kx16
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O
8R-15R
I/O
0R-7R
R/W
R
CE
0R
CE
1R
UB
R
LB
R
OE
R
CONTROL
LOGIC
CONTROL
LOGIC
A
13L
A
0L(1)
ADDRESS
DECODE
ADDRESS
DECODE
A
13R
A
0R(1)
BA
1L
BA
0L
BANK
DECODE
MUX
16Kx16
MEMORY
ARRAY
(BANK 3)
MUX
BANK
DECODE
BA
1R
BA
0R
BKSEL
3(2)
BKSEL
0(2)
BANK
SELECT
A
5L(1)
A
0L(1)
LB
L
/UB
L
OE
L
R/W
L
CE
L
MAILBOX
INTERRUPT
LOGIC
A
5R(1)
A
0R(1)
LB
R
/UB
R
OE
R
R/W
R
CE
R
MBSEL
L
INT
L
MBSEL
R
INT
R
3592 drw 01
NOTES:
1. The first six address pins for each port serve dual functions. When
MBSEL
= V
IH
, the pins serve as memory address inputs. When
MBSEL
= V
IL
, the pins
serve as mailbox address inputs.
2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for
more details.
MAY 2000
1
©2000 Integrated Device Technology, Inc.
DSC 3592/7
IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-Switchable
Dual-Ported SRAM organized into four independent 16K x 16 banks. The
device has two independent ports with separate control, address, and
I/O pins for each port, allowing each port to asynchronously access
any 16K x 16 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via bank select pin
inputs under the user's control. Mailboxes are provided to allow inter-
processor communication. Interrupts are provided to indicate mailbox
writes have occurred. An automatic power down feature controlled by
the chip enables (CE
0
and CE
1
) permits the on-chip circuitry of each port
to enter a very low standby power mode and allows fast depth expansion.
The IDT707288 offers a maximum address-to-data access time as fast
as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP).
IV). Once a bank is assigned to a particular port, the port has full access
to read and write within that bank. Each port can be assigned as many
banks within the array as needed, up to and including all four banks.
The IDT707288 provides mailboxes to allow inter-processor commu-
nication. Each port has four 16-bit mailbox registers available to which it
can write and read and which the opposite port can read only. These
mailboxes are external to the common SRAM array, and are accessed
by setting
MBSEL
= V
IL
while setting
CE
= V
IH
. Each mailbox has an
associated interrupt: a port can generate an interrupt to the opposite port
by writing to the upper byte of any one of its four 16-bit mailboxes. The
interrupted port can clear the interrupt by reading the upper byte. This read
will not alter the contents of the mailbox.
If desired, any source of interrupt can be independently masked via
software. Two registers are provided to permit interpretation of interrupts:
the Interrupt Cause Register and the Interrupt Status Register. The
Interrupt Cause Register gives the user a snapshot of what has caused
the interrupt to be generated - the specific mailbox written to. The
information in this register provides post-mask signals: interrupt sources
that have been masked will not be updated. The Interrupt Status Register
gives the user the status of all bits that could potentially cause an interrupt
regardless of whether they have been masked. Truth Table V gives a
detailed explanation of the use of these registers.
Functionality
The IDT707288 is a high-speed asynchronous 64K x 16 Bank-
Switchable Dual-Ported SRAM, organized in four 16K x 16 banks. The
two ports are permitted independent, simultaneous access into separate
banks within the shared array. There are four user-controlled Bank Select
input pins, and each of these pins is associated with a specific bank within
the memory array. Access to a specific bank is gained by placing the
associated Bank Select pin in the appropriate state: V
IH
assigns the bank
to the left port, and V
IL
assigns the bank to the right port (See Truth Table
6.42
2
IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
INDEX
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
13L
NC
BKSEL
0
LB
L
UB
L
CE
0L
CE
1L
MBSEL
L
Vcc
R/W
L
OE
L
GND
GND
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
BA
1L
BA
0L
A
12L
NC
BKSEL
1
INT
L
GND
GND
INT
R
BKSEL
2
A
12R
BA
0R
BA
1R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
IDT707288PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
A
6R
A
7R
A
8R
A
9R
A
10R
A
11R
A
13R
NC
BKSEL
3
LB
R
UB
R
CE
0R
CE
1R
MBSEL
R
GND
R/W
R
OE
R
GND
GND
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
3592 drw 02
Pin Configurations
(1,2,3)
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
Vcc
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O1
L
I/O
0L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
Vcc
I/O
7R
I/O
8R
I/O
9R
NC
,
Pin Names
A
0
- A
13
(1,6)
BA
0
- BA
1
(1)
MBSEL
(1)
BKSEL
0-3
(2)
R/W
(1)
OE
(1)
CE
0
,
CE
1
(1)
UB, LB
(1)
I/O
0
- I/O
15
(1)
INT
(1)
V
CC
(4)
GND
(5)
Address Inputs
Bank Address Inputs
Mailbox Access Control Gate
Bank Select Inputs
Read/Write Enable
Output Enable
Chip Enables
I/O Byte Enables
Bidirectional Data Input/Output
Interrupt Flag (Output)
(3)
+5VPower
Ground
3592 tbl 01
NOTES:
1. Duplicated per port.
2. Each bank has an input pin assigned that allows the user to toggle the assignment
of that bank between the two ports. Refer to Truth Table IV for more details. When
changing the bank assignments, accesses of the affected banks must be
suspended. Accesses may continue uninterrupted in banks that are not being
reallocted.
3. Generated upon mailbox access.
4. All Vcc pins must be connected to power supply.
5. All GND pins must be connected to ground supply.
6. The first six address pins (A
0
-A
5
) for each port serve dual functions. When
MBSEL
= V
IH
, the pins serve as memory address inputs. When
MBSEL
= V
IL
, the pins
serve as mailbox address inputs (A
6
-A
13
are ignored).
3
6.42
IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I Chip Enable
(1,2,3,4)
CE
CE
0
V
IL
L
< 0.2V
V
IH
H
X
>V
CC
-0.2V
X
CE
1
V
IH
>V
CC
-0.2V
X
V
IL
X
<0.2V
Port Selected (TTL Active)
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
3592 tbl 02
Mode
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels;
CE
is a reference only.
2. Port "A" and "B" references are located where
CE
is used.
3. "H" = V
IH
and "L" = V
IL
.
4.
CE
and
MBSEL
cannot both be active at the same time.
Truth Table II Non-Contention Read/Write Control
Inputs
(1)
CE
(2)
H
X
(3)
L
L
L
L
L
L
X
(3)
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
MBSEL
H
X
(3)
H
H
H
H
H
H
X
(3)
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
Outputs
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Deselcted: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
3592 tbl 03
Mode
NOTES:
1. BA
0L
- BA
1L
≠
BA
0R
- BA
1R
: cannot access same bank simultaneously from both ports.
2. Refer to Truth Table I.
3.
CE
and
MBSEL
cannot both be active at the same time.
Truth Table III Mailbox Read/Write Contro
l
(1)
Inputs
CE
(2)
H
H
H
L
R/W
H
H
L
X
OE
L
L
X
X
UB
X
(3)
L
L
(3)
X
LB
X
(3)
L
L
(3)
X
MBSEL
L
L
L
L
I/O
8-15
DATA
OUT
DATA
OUT
DATA
IN
____
Outputs
I/O
0-7
DATA
OUT
DATA
OUT
DATA
IN
____
Mode
Read Data from Mailbox,
↓
clears interrupt
Read Data from Mailbox,
↓
clears interrupt
Write Data into Mailbox
Not Allowed
3592 tbl 04
NOTES:
1. There are four mailbox locations per port written to and read from all the I/O's (I/O
0
-I/O
15
). These four mailboxes are addressed by A
0
-A
5.
Refer to Truth Table V.
2. Refer to Truth Table I.
3. Each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to
UB
and
LB
appropriately.
6.42
4
IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
3592 tbl 06
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
Industrial
o
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
mA
3592 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
3592 tbl 07
____
Capacitance
(1)
Symbol
C
IN
C
OUT
(3)
(T
A
= +25°C, f = 1.0mhz) TQFP Package
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
3592 tbl 08
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
3. C
OUT
represents C
I/O
as well.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
707288S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
,
MBSEL
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
707288L
Min.
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3592 tbl 09
___
___
___
___
2.4
2.4
NOTE:
1. At Vcc
<
2.0V, input leakages are undefined.
5
6.42
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