HIGH-SPEED
4K x 18 DUAL-PORT
STATIC RAM
Features:
x
x
IDT7034S/L
x
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
Commercial: 15/20ns (max.)
Low-power operation
IDT7034S
Active: 850mW (typ.)
Standby: 5mW (typ.)
IDT7034L
Active: 850mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT7034 easily expands data bus width to 36 bits or more
x
x
x
x
x
x
x
x
x
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Industrial temperature range (40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
BUSY
L
(1,2)
I/O
Control
I/O
Control
I/O
9R
-I/O
17R
I/O
0R
-I/O
8R
BUSY
R
(1,2)
.
A
11L
A
0L
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
A
11R
A
0R
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
(2)
INT
R
4089 drw 01
M/
S
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
SEPTEMBER 1999
1
©1999 Integrated Device Technology, Inc.
DSC 4089/6
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT7034 is a high-speed 4K x 18 Dual-Port Static RAM. The
IDT7034 is designed to be used as a stand-alone 72K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit
or more word systems. Using the IDT MASTER/SLAVE Dual-Port
RAM approach in 36-bit or wider memory system applications results
in full-speed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power down
feature controlled by Chip Enable (CE) permits the on-chip circuitry of each
port to enter a very low standby power mode.
The IDT7034 utilizes a 18-bit wide data path to allow for parity at
the user's option. This feature is especially useful in data communica-
tion applications.
Fabricated using IDTs CMOS high-performance technology, these
devices typically operate on only 850mW of power. Low-power (L)
versions offer battery backup data retention capability with typical
power consumption of 500µW from a 2V battery.
Pin Configurations
(1,2,3)
Index
N/C
N/C
I/O
8L
I/O
17L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
GND
I/O
15L
I/O
16L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
8R
I/O
17R
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
74
73
72
71
70
69
68
67
I/O
10L
I/O
9L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
OE
L
V
CC
R/W
L
SEM
L
CE
L
UB
L
LB
L
N/C
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
IDT7034PF
PN100-1
(4)
100-PIN TQFP
TOP VIEW
(5)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
.
I/O
7R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
I/O
16R
OE
R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
N/C
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
NOTES:
1. All V
CC
pins must be connected to power supply
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
4089drw 02
2
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
11L
I/O
0L
- I/O
17L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
11R
I/O
0R
- I/O
17R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/S
V
CC
GND
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
4089 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
X
L
L
L
L
L
L
X
NOTE:
Outputs
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
9-17
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
I/O
0-8
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
4089 tbl 02
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
1. A
0L
A
11L
≠
A
0R
A
11R
3
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
H
X
H
X
L
L
R/W
H
H
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
9-17
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Outputs
I/O
0-8
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
4089 tbl 03
↑
↑
X
X
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0
- I/O
17.
These eight semaphores are addressed by A
0
- A
2
.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
Maximum Operating
Temperature and Supply
Voltage
(1,2)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
4089 tbl 05
V
T
BIAS
T
STG
I
OUT
-55 to +125
-55 to +125
50
o
C
C
o
mA
4089 tbl 04
NOTES:
1. This is the parameter T
A
.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20 mA for the period over V
TERM
> Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
4089 tbl 06
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
(1)
____
Max.
9
10
Unit
pF
pF
4089 tbl 07
V
IN
= 3dV
V
OUT
= 3dV
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
4
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
7034S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
Min.
___
___
___
7034L
Max.
10
10
0.4
___
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
4089 tbl 08
2.4
2.4
NOTE:
1. At V
CC
< 2.0V input leakages are undefined.
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1,6)
(V
CC
= 5.0V ± 10%)
7034X15
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Open
SEM
= V
IH
f = f
MAX
(3)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(2)
170
170
170
170
20
20
20
20
105
105
105
105
1.0
0.2
1.0
0.2
100
100
100
100
Max.
310
260
390
330
60
50
90
70
190
160
250
220
15
5
30
10
170
140
245
210
7034X20
Com'l Only
Typ.
(2)
160
160
160
160
20
20
20
20
95
95
95
95
1.0
0.2
1.0
0.2
90
90
90
90
Max.
290
240
370
320
60
50
90
70
180
150
240
210
15
5
30
10
155
130
225
200
4089 tbl 09
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(3)
mA
I
SB2
Standby Current
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
(One Port - TTL Level Inputs) Active Port Outputs Open,
f=f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Open
f = f
MAX
(3)
mA
I
SB3
mA
I
SB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
mA
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. V
CC
= 5V, T
A
= +25°C, and are not production tested. Icc dc
=
120mA (TYP)
3. At f = f
MAX
,
address and I/O'
S
are cycling at the maximum frequency read cycle of 1/t
RC
, and using AC Test Conditions of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
5
6.42
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
