Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
Precision supply-voltage monitor
-
-
-
-
-
4.63V (PT7A7511, 7521, 7531)
4.38V (PT7A7512, 7522, 7532)
3.08V (PT7A7513, 7523, 7533)
2.93V (PT7A7514, 7524, 7534)
2.63V (PT7A7515, 7525, 7535)
Description
The PT7A751X/752X/753X family microprocessor
(µP) supervisory circuits are targeted to improve
reliability and accuracy of power-supply circuitry in
µP’s
systems. These devices reduce the complexity and
number of components required to monitor power-
supply and battery functions.
The main functions are:
1. Asserting reset output during power-up, power-
down and brownout conditions for
µP
system.
2. Detecting power failure or low-battery
conditions with a 1.25V threshold detector.
3. Watchdog functions (not for PT7A753x)
200ms reset pulse width
Debounced TTL/CMOS-compatible manual-
reset input
Independent watchdog timer 1.6sec time-out (not
available for PT7A7531 - 7535)
Reset output signal:
- Active-low only (PT7A7511 - 7515)
-
-
Active-high only (PT7A7521 - 7525)
Active-high and active-low (PT7A7531 - 7535)
warning
Guaranteed RESET/RESET valid at V
CC
=1.2V
Applications
Power-supply circuitry in
µP
systems
Voltage monitor for power-fail or low battery
Ordering Information
Part Number
PT7A751xPE
PT7A752xPE
PT7A753xPE
Package
Lead free DIP-8
Lead free DIP-8
Lead free DIP-8
Part Number
PT7A751xWE
PT7A752xWE
PT7A753xWE
Package
Lead free and Green SOIC-8
Lead free and Green SOIC-8
Lead free and Green SOIC-8
Note:
“X” refers to voltage range, see below table.
Suffix: X—Monitored Voltage and Function Comparison
Part No.
PT7A7511
PT7A7521
PT7A7531
PT7A7512
PT7A7522
PT7A7532
PT7A7513
PT7A7523
PT7A7533
PT7A7514
PT7A7524
PT7A7534
PT7A7515
PT7A7525
PT7A7535
PT0082(10/10)
1
Reset
Threshold
4.63V
4.63V
4.63V
4.38V
4.38V
4.38V
3.08V
3.08V
3.08V
2.93V
2.93V
2.93V
2.63V
2.63V
2.63V
Reset Active
Low or High
LOW
HIGH
LOW, HIGH
LOW
HIGH
LOW, HIGH
LOW
HIGH
LOW, HIGH
LOW
HIGH
LOW, HIGH
LOW
HIGH
LOW, HIGH
Nom. Reset
Time (ms), t
RS
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
Nom. Watch dog
Time (sec), t
WD
1.6
1.6
unavailable
1.6
1.6
unavailable
1.6
1.6
unavailable
1.6
1.6
unavailable
1.6
1.6
unavailable
Power Fail
Comp.
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
1.25V detector
Manual
Reset Input
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Ver: 7
Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Block Diagram
Block Diagram of PT7A7511-7515/7521-7525
WDI
Watchdog
Transition Detector
Vcc
250uA
Watchdog Timer
Timebase for Reset
& Watchdog
WDO
MR
Reset Generator
Vcc
RESET
(RESET)
V
RST
PFI
1.25V
PFO
Block Diagram of PT7A7531-35
Vcc
250uA
MR
Vcc
Reset Generator
RESET
RESET
V
RST
PFI
PFO
1.25V
PT0082(10/10)
2
Ver: 7
Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Configuration
PT7A7511P-7515P
PT7A7511W-7515W
8-Pin PDIP/8-Pin SOIC
MR
V
CC
GND
PFI
1
2
3
4
8
7
6
5
WDO
RESET
WDI
PFO
MR
V
CC
GND
PFI
PT7A7521P-7525P
PT7A7521W-7525W
8-Pin PDIP/8-Pin SOIC
1
2
3
4
8
7
6
5
WDO
RESET
WDI
PFO
MR
V
CC
GND
PFI
PT7A7531P-7535P
PT7A7531W-7535W
8-Pin PDIP/8-Pin SOIC
1
2
3
4
8
7
6
5
RESET
RESET
NC
PFO
Top View
Pin Description
Pin
MR
V
CC
GND
PFI
PFO
Type
I
Power
Ground
I
O
Description
Manual-Reset:
triggers a reset pulse when pulled below 0.8V, active low. It has an internal 250mA pull-
up current and be driven from a TTL or CMOS logic line as well as shorted to ground with a switch.
Supply Voltage.
Ground Reference
for all signals.
Power-Fail Voltage Monitor Input.
When PFI is less than 1.25V, PFO goes low. Connect PFI to GND
or Vcc when not used.
Power-Fail Output:
it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high.
Watchdog Input:
If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and WDO
goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the watchdog
feature. The internal watchdog timer clears whenever reset is asserted. WDI is three-stated, or WDI sees a
rising or falling edge.
Reset Output pulses:
low for 200ms when triggered, and stays low whenever Vcc is below the reset
threshold. It remains low for 200ms after Vcc rises above the reset threshold or MR goes from low to
high. A watchdog timeout will not trigger RESET unless WDO is connected to MR.
Watchdog Output:
pulls low when the internal watchdog timer finishes its 1.6sec count and does not go
high again until the watchdog is cleared. WDO also goes low during low-line conditions. Whenever Vcc
is below the reset threshold, WDO stays low; however, unlike RESET, WDO does not have minimum
pulse width. As soon as Vcc rises above the reset threshold, WDO goes high with no delay.
The inverse of RESET,
active high. Whenever RESET is high, RESET is low.
WDI
I
RESET
O
WDO
O
O
RESET
PT0082(10/10)
3
Ver: 7
Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Functional Description
The PT75xx family can assert reset output during power-up, power-down and brownout conditions for
µP
system, detect power
failure or low-battery conditions with a 1.25V threshold detector and have watchdog functions. Refer to Function Table of
PT7A75xx Family for their individual features. The typical application see Figure 4.
Reset Output
The supervisory circuits can assert reset for a microprocessor during power-up, power-down and brownout to prevent code
execution errors.
On power-up, once Vcc reaches about 1.2V, RESET is a guaranteed logic low of 0.4V or less. As Vcc rises, RESET stays low.
When Vcc rises above the reset threshold, an internal timer releases RESET after about 200ms. RESET pulses low whenever Vcc
drops below the reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the
pulse continues for at least another 140ms. On power-down, once Vcc falls below the reset threshold, RESET stays low and is
guaranteed to be 0.4V or less until Vcc drops below 1.0V.
The PT7A752x and PT7A753x active-high RESET output is simply the inverse of the RESET output, and is guaranteed to be
valid with Vcc down to 1.2V. Some
µPs,
such as Intel’s 80C51, require an active-high reset pulse.
Watchdog Timer
The watchdog circuit monitors the
µP
activity. If the
µP
does not toggle the watchdog input (WDI) within 1.6sec and WDI is not
in high impedance, WDO goes low. As long as RESET is asserted or the WDI input is in high impedance, the watchdog timer will
stay cleared and will not count. As soon as reset is released and WDI is driven high or low, the timer will start counting. Pulses as
short as 50ns can be detected.
Typically, WDO will be connected to the non-maskable interrupt input (NMI) of a
µP.
When VCC drops below the reset
threshold, WDO will go low whether or not the watchdog timer has timed out yet. Normally this would trigger an NMI interrupt,
but RESET goes low simultaneously, and thus overrides the NMI interrupt. If WDI is left unconnected, WDO can be used as a
low-line output. Since floating WDI disables the internal timer, WDO goes low only when VCC falls below the reset threshold,
thus functioning as a low-line output.
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a push button switch. The switch is effectively debounced by the
140ms minimum reset pulse width. MR is TTL/CMOS logic compatible, so it can be driven by any logic reset output.
Power-Fail Comparator
The power-fail comparator will send out a Low signal once detects a voltage lowered than 1.25V. It can be used for various
purposes because its output and non-inverting input are not internally connected. The inverting input is internally connected to a
1.25V reference..
Typical Application Circuit
IN
DC Linear
Regulator
OUT
Vcc
RESET
µP
Supervisory
Circuit
PFI
WDI
WDO
MR
PFO
Vcc
RESET
I/O Line
NMI
Interrupt
µP
PT0082(10/10)
4
Ver: 7
Data Sheet
PT7A7511-15/7521-25/7531-35
µP Supervisor Circuits
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Maximum Ratings
Storage Temperature ............................................................-65
o
C to +150
o
C
Ambient Temperature with Power Applied.......................... -40
o
C to +85
o
C
Supply Voltage to Ground Potential (Vcc to GND) ..............-0.3V to +7.0V
DC Input Voltage (All inputs except Vcc and GND)......-0.3V to V
CC
+0.3V
DC Output Current (All outputs) ..........................................................20mA
Power Dissipation .......................................... 500mW (Depend on package)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Recommended Operation Conditions
Sym
V
CC
V
IH1
V
IH2
V
IL1
V
IL2
T
A
Description
Supply Voltage for 75x1,75x2
Supply Voltage for 75x3,75x4
Supply Voltage for 75x5
MR Input High Voltage
WDI Input High Voltage
MR Input Low Voltage
WDI Input Low Voltage
Operating Temperature
Test Conditions
-
-
V
CC
> 4.0V
V
CC
≤
4.0V
-
V
CC
> 4.0V
V
CC
≤
4.0V
-
-
Min
4.5
3.0
2.7
2.0
0.7V
CC
0.7V
CC
-
-
-
-40
Typ
5.0
3.3
3.0
2.4
-
-
-
-
-
-
Max
5.5
5.5
5.5
-
-
-
0.8
0.2V
CC
0.3V
CC
85
Unit
V
V
V
V
V
V
V
V
℃
PT0082(10/10)
5
Ver: 7
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
