Data Sheet
PT7A6525/6525L/6526 HDLC Controller
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Features
Serial Interface
•
Supports two independent full-duplex HDLC
channels (PT7A6526: one channel,
PT7A6525/6525L: two channels)
- On-chip clock generation or external clock
source
- On-chip DPLL type clock recovery for each
channel
- Two independent baud-rate generators
(PT7A6526: one baudrate generator)
- Independent time-slot assignment for each
channel with programmable time-slot length
(1 to 256 bit)
•
•
•
•
•
•
•
•
•
Provides up to 64 bytes each for Transmit
Receive FIFOs
Various data encoding modes
Modem control lines (RTS, CTS, CD)
Supports bus configuration by Collision
Resolution
Programmable bit inversion
Data rate up to 8Mb/s
Transparent Mode selectable
Power Supply: 5V (6525/6526) or 3.3V (6525L)
Available Package: 44-pin PLCC and 44-pin
MQFP (PT7A6525 only)
and
•
•
•
•
•
•
Protocol Support
•
Supports LAPB/LAPD/SDLC/HDLC protocol
in Auto Mode
Handles Bit-Oriented functions in all modes
Modulo-8 or modulo-128 operation
Programmable maximum packet size checking
Programmable time-out and retry conditions
Microprocessor Interface
•
Efficient transfer of data blocks by DMA or
Interrupt Request
8-bit demultiplexed or multiplexed bus interface
Suitable for Intel or Motorola microprocessor
Ordering Information
P a r t N o.
PT7A6525J
PT7A6525LJ
PT7A6526J
PT7A6525M
PT7A6525JE
PT7A6525LJE
PT7A6526JE
Pa ck a ge
44- Pin PLCC
44- Pin PLCC
44- Pin PLCC
44- Pin MQFP
Lead free 44- Pin PLCC
Lead free 44- Pin PLCC
Lead free 44- Pin PLCC
Applications
•
•
•
•
•
Data link controller and protocol generators
Digital sets, PBXs and private packet networks
C-channel controller of data network interface
circuits
D-channel controller for ISDN basic access
Interprocessor communications
PT0017(12/05)
1
Ver:8
Data Sheet
PT7A6525/6525L/6526 HDLC Controller
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Introduction
The PT7A6525/6525L/6526 are designed to implement
high-speed communication links using HDLC protocols.
They profoundly reduce the hardware and software
overhead needed for serial synchronous communications.
The PT7A6525/6525L supports two completely
independent full-duplex HDLC channels (channel A and
channel B), while the PT7A6526 supports only one
(channel B). For each channel, there are an internal
Oscillator, Baud-Rate Generator (BRG), Digital Phase-
Locked Loop (DPLL), Time-Slot Assignment (TSA)
Circuitry, and a Link Controller to support various layer-
1 functions. They also directly support the X.25 LAPB,
the ISDN LAPD and SDLC (normal response mode)
protocols and are capable of handling a large set of layer-
2 protocol functions independently.
A variety of programmable telecom-specific features
The data link controller handles all functions necessary
to establish and maintain an HDLC data link, such as
allow the PT7A6525/6525L/6526 to be widely used in
time-slot oriented PCM systems, systems designed for
packet switching, and ISDN applications.
Associated with each serial channel are its own separate
transmit and receive DMA request lines. Thus, the
PT7A6525/6525L has a 4-channel DMA interface.
- Flag insertion and detection,
- Bit stuffing,
- CRC generation and checking, and
- Address field recognition.
Associated with each serial channel are a set of
independent command and status registers and 64-byte
FIFOs each for the transmit and receive directions. Data
blocks from / to system memory can be transferred by
either Interrupt Request or Direct Memory Access
(DMA).
PT0017(12/05)
2
Ver:8
Data Sheet
PT7A6525/6525L/6526 HDLC Controller
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Contents
Features ............................................................................................................................... 1
Applications ........................................................................................................................ 1
Introduction ........................................................................................................................ 2
Block Diagram .................................................................................................................... 4
Pin Information ................................................................................................................... 5
Pin Assignment .................................................................................................................................... 5
Pin Configuration ................................................................................................................................. 6
Pin Description .................................................................................................................................... 7
Functional Description ............................................................................................. 10
General ............................................................................................................................................. 10
Modes of Operation .......................................................................................................................... 12
Procedural Support (Layer-2 Functions) ............................................................................................ 15
Data Transfer Modes ........................................................................................................................ 19
FIFO Structure ................................................................................................................................. 20
Clock Modes .................................................................................................................................... 22
Bus Configuration .............................................................................................................................. 26
Data Encoding .................................................................................................................................. 27
Special Functions .............................................................................................................................. 27
Operational Description ..................................................................................................................... 29
Registers ........................................................................................................................................... 36
Detailed Specifications ............................................................................................ 54
Absolute Maximum Ratings ............................................................................................................... 54
DC Electrical Chacarteristics ............................................................................................................. 55
AC Electrical Characteristics ............................................................................................................. 56
Power Supply and Capacitance Characteristics .................................................................................. 56
Quartz Crystal Specifications ............................................................................................................. 66
Mechanical Information ..................................................................................................................... 67
Appendix: Index of Registers ................................................................................... 70
Notes ................................................................................................................................. 71
PT0017(12/05)
3
Ver:8
Data Sheet
PT7A6525/6525L/6526 HDLC Controller
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Block Diagram
Figure 1. Block Diagram
Channel A
A0~A6
D0~D7
RD/IC1
WR/IC0
CS
ALE/IM0
RxCLKA
INT
RES
IM1
Receive
FIFO
Clock
Controller
AxCLKA
TxCLKA
Micro
Processor
Interface
Transmit
FIFO
Data
Link
Controller
Collision
Detector
RxDA
TxDA
RTSA
CTSA/CxDA
RxDB
DRQTA
DRQRA
DACKA
DMA
Controller
Transmit
FIFO
Data
Link
Controller
Collision
Detector
TxDB
RTSB
CTSB/CxDB
RxCLKB
DRQTB
DRQRB
DACKB
Channel B
Receive
FIFO
Clock
Controller
AxCLKB
TxCLKB
PT0017(12/05)
4
Ver:8
Data Sheet
PT7A6525/6525L/6526 HDLC Controller
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Pin Information
Pin Assignment
Table1. Pin Assignment
G r ou p
Chip Clock
Power & Ground
Microprocessor Interface
I/O Interface
DMA Interface
Others
Sym b ol
AxCLKA, AxCLKB, TxCLKA,
TxCLKB, RxCLKA, RxCLKB
GND, V
CC
D0-D7, A0-A6, RD/IC1, WR/IC0, CS,
ALE/IM0, INT, RES, IM1
RxDA, TxDA, TxDB, RxDB
DRQTA, DRQRA, DACKA, DACKB,
DRQTB, DRQRB
RTSA, CTSA/CxDA, CTSB/CxDB,
RTSB
F u n ct ion
Clock
Power
Data or Control
Serial Data
DMA Control
Depending on Bus Configurations
PT0017(12/05)
5
Ver:8
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