FUJITSU SEMICONDUCTOR
DATA SHEET
AE0.2E
MEMORY
CMOS
256M BIT
DOUBLE DATA RATE FCRAM™
MB81N26847B/261647B
-50/-55/-60
CMOS 4-BANK x 67,108,864 BIT
Fast Cycle Random Access Memory
with Double Data Rate
s
DESCRIPTION
The Fujitsu MB81N26847B/261647B is a CMOS Fast Cycle Random Access Memory (FCRAM) containing
268,435,456 memory cells accessible in an 8-bit or 16-bit format. The MB81N26847B/261647B features a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81N26847B/261647B is designed to
reduce the complexity of using a standard Dynamic RAM (DRAM) which requires many control signal timing
constraints. The MB81N26847B/261647B uses Double Data Rate (DDR) where data bandwidth is twice of fast
speed compared with regular SDRAMs.
The MB81N26847B/261647B is designed using Fujitsu advanced FCRAM Core Technology.
The MB81N26847B/261647B is ideally suited for Enterprise Servers, Network Systems, Hardware Accelerators,
Buffers, and other applications where large memory density and high effective bandwidth are required and where
a simple interface is needed.
The MB81N26847B/261647B adopts CMOS I/O interface circuitry, 2.5 V SSTL-2 interface, which is capable of
extremely fast data transfer of quality.
s
PRODUCT LINE
Parameter
Clock Frequency
Random Access Time
Random Address Cycle Time
DQS Access Time From Clock
Operating Current (I
DD1S
)
Power Down Current (I
DD2P
)
CL = 4
CL = 3
MB81N26847B/261647B
-50
200 MHz max
183 MHz max
22 ns max
25 ns min
+/– 0.75 ns max
190 mA max
2 mA max
-55
183 MHz max
166 MHz max
24 ns max
27.5 ns min
+/– 0.75 ns max
180 mA max
2 mA max
-60
166 MHz max
154 MHz max
26 ns max
30 ns min
+/– 0.85 ns max
170 mA max
2 mA max
Notice: FCRAM is a trademark of Fujitsu Limited, Japan.
(AE0.2E) 1
MB81N26847B/261647B-50/-55/-60
s
FEATURES
•
•
•
•
•
Double Data Rate
Bi-directional Data Strobe Signal
Four independent bank operation
Burst read/write operation
Programmable burst type, burst length,
CAS latency and output driver strength
•
•
•
•
•
ADVANCE INFO.
Variable Write Length Control per Byte
Distributed Auto-refresh cycle in 7.8
µs
2.5 V CMOS I/O comply with SSTL_2
V
DD
:
+2.5V Supply ± 0.15V tolerance
V
DDQ
: +2.5V Supply ± 0.15V tolerance
s
PACKAGE
Plastic TSOP(II) Package
(FPT-66P-Mxx)
(Normal Bend)
Package and Ordering Information
– 66-pin plastic (400 mil) TSOP-II, order as MB81N26847B/261647B-××FN
2 (AE0.2E)
MB81N26847B/261647B-50/-55/-60
s
PIN ASSIGNMENTS AND DESCRIPTIONS #1
Fig. 1 – MB81N26847B PIN ASSIGNMENTS
66-Pin TSOP(II)
(TOP VIEW)
V
DD
DQ
0
V
DDQ
NC2
DQ
1
V
SSQ
NC2
DQ
2
V
DDQ
NC2
DQ
3
V
SSQ
NC2
NC1
V
DDQ
NC2
NC1
V
DD
NC1
NC1
A
14
A
13
FN
CS
NC1
BA
0
BA
1
A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
ADVANCE INFO.
V
SS
DQ
7
V
SSQ
NC2
DQ
6
V
DDQ
NC2
DQ
5
V
SSQ
NC2
DQ
4
V
DDQ
NC2
NC1
V
SSQ
DQS
NC1
V
REF
V
SS
NC1
CLK
CLK
PD
NC1
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Number
1, 3, 9, 15, 18, 33, 55, 61
2, 5, 8, 11, 56, 59, 62, 65
6, 12, 34, 48, 52, 58, 64, 66
21, 22, 28, 29, 30, 31, 32, 35, 36, 37, 38, 39, 40, 41, 42
23
24
26, 27
44
45
46
49
51
14, 17, 19, 20, 25, 43, 47, 50, 53
4, 7, 10, 13, 16, 54, 57, 60, 63
Symbol
V
DD
, V
DDQ
DQ
0
to DQ
7
V
SS
, V
SSQ
A
0
to A
14
FN
CS
BA
1
, BA
0
PD
CLK
CLK
V
REF
DQS
NC1
NC2
Supply Voltage
Data I/O
Ground
Address Input
Function Select
Chip Select
Bank Address
Power Down
Clock Input
Clock Input
Function
• Upper: A
0
to A
14
• Lower: A
0
to A
7
Input Reference Voltage
Data Strobe
No Connection
No Connection (Left Open)
(AE0.2E) 3
MB81N26847B/261647B-50/-55/-60
s
PIN ASSIGNMENTS AND DESCRIPTIONS #2
ADVANCE INFO.
Fig. 2 – MB81N261647B PIN ASSIGNMENTS
66-Pin TSOP(II)
(TOP VIEW)
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC1
V
DDQ
LDQS
NC1
V
DD
NC1
NC1
A
14
A
13
FN
CS
NC1
BA
0
BA
1
A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC1
V
SSQ
UDQS
NC1
V
REF
V
SS
NC1
CLK
CLK
PD
NC1
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Number
1, 3, 9, 15, 18, 33, 55, 61
2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65
6, 12, 34, 48, 52, 58, 64, 66
21, 22, 28, 29, 30, 31, 32, 35, 36, 37, 38, 39, 40, 41, 42
23
24
26, 27
44
45
46
49
16
51
14, 17, 19, 20, 25, 43, 47, 50, 53
Symbol
V
DD
, V
DDQ
DQ
0
to DQ
15
V
SS
, V
SSQ
A
0
to A
14
FN
CS
BA
1
, BA
0
PD
CLK
CLK
V
REF
LDQS
UDQS
NC1
Supply Voltage
Data I/O
Ground
Address Input
Function Select
Chip Select
Bank Address
Power Down
Clock Input
Clock Input
Function
• Upper: DQ
8
to DQ
15
• Lower: DQ
0
to DQ
7
• Upper: A
0
to A
14
• Lower: A
0
to A
6
Input Reference Voltage
Lower Byte Data Strobe
Upper Byte Data Strobe
No Connection
4 (AE0.2E)
MB81N26847B/261647B-50/-55/-60
s
BLOCK DIAGRAM #1
Fig. 3 – MB81N26847B BLOCK DIAGRAM
ADVANCE INFO.
CLK
CLK
PD
CLOCK
BUFFER
To each block
Bank-3
Bank-2
Enable
..
.
Bank-1
Bank-0
CS
CS
CONTROL
SIGNAL
LATCH
COMMAND
DECODER
R/W
FN
DRAM
MODE
REGISTER
CORE
(8M x 8)
ADDRESS
23
A
0
to A
14
BURST
ACCESS
COUNTER
DQ
0
to
DQ
7
DQS
..
BA
0
,BA
1
.
ADDRESS
BUFFER/
REGISTER
2
BURST
ADDRESS
I/O
I/O DATA
BUFFER/
REGISTER
&
DQS
GENERA-
TOR
8
DLL
Clock Buffer
V
DD
V
REF
V
SS
/ V
SSQ
V
DDQ
, V
SSQ
(AE0.2E) 5
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