DATASHEET
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Description
The MK2069-04 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that features a PLL
(Phase-Locked Loop) input reference divider and feedback
divider that have a wide numeric range selectable by the
user. This enables a complex PLL multiplication ratio that
can be used for translation between clock frequency
standards.
The on-chip VCXO produces a stable, low jitter output clock
using a phase detector frequency down to 8 kHz or lower.
This means the MK2069-04 can translate between clock
frequencies that have a low common denominator, such as
the 8 kHz frame clock common with telecom standards. The
MK2069-04 also provides jitter attenuation of the input
clock and can accept a low input frequency as well.
The device is optimized for user configurability by providing
access to all major PLL divider functions. No power-up
programming is needed as configuration is pin selected.
External VCXO loop filter components provide an additional
level of user configurability.
The MK2069-04 includes a lock detector (LD) output that
serves as a clock status monitor. The clear (CLR) input
enables rapid synchronization to the phase of a newly
selected input clock.
MK2069-04
Features
•
Input clock frequency <1 kHz to 170 MHz
•
Output clock frequency of 500 kHz to 160 MHz
•
Clock translation examples:
T1 (1.544 MHz) to/from E1 (2.048 MHz)
T3 (44.736 MHz) to/from E3 (34.368 MHz)
OC-3 (155.52 MHz) to/from T1 (1.544 MHz)
CCIR-601 (27 MHz) to/from SMPTE 274M (74.125
MHz)
•
Jitter attenuation of input clock provided by VCXO circuit.
•
•
•
•
•
•
•
•
•
Jitter transfer characteristics user configured through
external loop filter component selection.
Low jitter and phase noise generation.
PLL lock status output
PLL Clear function allows seamless synchronizing to an
altered input clock phase
2nd PLL provides frequency translation of VCXO PLL
output (VCLK) to a higher or alternate output frequency
(TCLK).
Device will free-run in the absence of an input clock
based on VCXO frequency.
56-pin TSSOP package
Single 3.3 V power supply
5 V tolerant clock input
Available in Pb (lead) free package
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
P u lla b le
x ta l
RPV
R V 1 1:0
12
S V 1 :0
IS E T
LF
LFR
X1
X2
2
ST
VDD
4
VCLK
P hase
D etector
O EV
VCXO
C harge
P um p
IC L K
RPV
D iv id er
1, 8
RV
D iv id e r
2 to 4 0 9 7
SV
D iv id e r
1 ,2 ,1 2,1 6
VCO
ST
D ivid e r
2, 16
TCLK
O ET
VCXO
PLL
F V D iv id er
1 to 4 09 6
F T D iv id e r
T ran s la to r
PLL
2 to 1 6 , e v e n o n ly
RCLK
L o c k D e te c to r
O ER
LD
CLR
O EL
12
LDC
LDR
3
4
F V 1 1 :0
F T 2 :0
GND
IDT™
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
1
MK2069-04
REV H 122109
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
Pin Assignment
RV5
RV6
RV7
RV8
FT0
FT1
FT2
RV9
R V10
R V11
ST
VDDT
GNDT
X1
VDDV
X2
GNDV
LFR
LF
IS E T
FV0
FV1
FV2
FV3
FV4
FV5
FV6
FV7
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
RPV
SV1
SV0
RV4
RV3
RV2
O EL
O ET
O EV
O ER
VDD
LD
TCLK
VDDP
VCLK
GNDP
RCLK
LDR
GND
LDC
CLR
IC L K
RV1
RV0
FV11
FV10
FV9
FV8
Input Selection Tables
VCXO PLL Reference Pre-Divider Selection Table
RPV RPV Pre-Divider Ratio
0
1
1
8
VCXO PLL Reference Divider Selection Table
RV11:0
0...00
0...01
:
1...11
RV Divider
Ratio
2
3
:
4097
Notes
M K 2 0 6 9 -0 4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RV Divide Value
= Address + 2
VCXO PLL Feedback Divider Selection
FV11:0 FV Divider Ratio
Notes
For FV addresses 0 to 4094,
0...00
2
FV Divide Value
0...01
3
= Address + 2
:
:
1...10
4096
1...11
1
VCXO PLL Scaling Divider Selection Table
SV1 SV0
0
0
0
1
1
0
1
1
SV Divider Ratio
12
2
16
1
Translator PLL Feedback Divider Selection
FT2
0
0
0
0
1
1
1
1
FT1
0
0
1
1
0
0
1
1
FT0
0
1
0
1
0
1
0
1
FT Divider Ratio
4
6
8
10
12
14
16
2
Translator PLL Scaling Divider Selection Table
ST
0
1
ST Divider Ratio
2
16
IDT™
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
2
MK2069-04
REV H 122109
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Pin
Name
RV5
RV6
RV7
RV8
FT0
FT1
FT2
RV9
RV10
RV11
ST
VDDT
GNDT
X1
VDDV
X2
GNDV
LFR
LF
ISET
FV0
FV1
FV2
FV3
FV4
FV5
FV6
FV7
FV8
FV9
FV10
FV11
RV0
RV1
ICLK
CLR
LDC
GND
LDR
RCLK
GNDP
Pin
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Ground
—
Power
—
Ground
—
—
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
Ground
Power
—
Ground
Pin Description
Reference Divider bit 5 input, VCXO PLL, internal pull-up.
Reference Divider bit 6 input, VCXO PLL, internal pull-up.
Reference Divider bit 7 input, VCXO PLL, internal pull-up.
Reference Divider bit 8 input, VCXO PLL, internal pull-up.
Feedback Divider bit 0 input, Translator PLL, internal pull-up.
Feedback Divider bit 1 input, Translator PLL, internal pull-up.
Feedback Divider bit 2 input, Translator PLL, internal pull-up.
Reference Divider bit 9, VCXO PLL, internal pull-up.
Reference Divider bit 10, VCXO PLL, internal pull-up.
Reference Divider bit 11, VCXO PLL, internal pull-up.
Scaling Divider selection bit, Translator PLL, internal pull-up.
Power Supply connection for translator PLL.
Ground connection for translator PLL.
Crystal oscillator input. Connect this pin to the external quartz crystal.
Power Supply connection for VCXO PLL.
Crystal oscillator output. Connect this pin to the external quartz crystal.
Ground connection for VCXO PLL.
Loop filter connection, reference node. Refer to loop filter circuit on page 6.
Loop filter connection, active node. Refer to loop filter circuit on page 6.
Charge pump current setting pin. Refer to loop filter circuit on page 6.
Feedback Divider bit 0 input, VCXO PLL, internal pull-up.
Feedback Divider bit 1input, VCXO PLL, internal pull-up.
Feedback Divider bit 2 input, VCXO PLL, internal pull-up.
Feedback Divider bit 3 input, VCXO PLL, internal pull-up.
Feedback Divider bit 4 input, VCXO PLL, internal pull-up.
Feedback Divider bit 5 input, VCXO PLL, internal pull-up.
Feedback Divider bit 6 input, VCXO PLL, internal pull-up.
Feedback Divider bit 7 input, VCXO PLL, internal pull-up.
Feedback Divider bit 8 input, VCXO PLL, internal pull-up.
Feedback Divider bit 9 input, VCXO PLL, internal pull-up.
Feedback Divider bit 10 input, VCXO PLL, internal pull-up.
Feedback Divider bit 11 input, VCXO PLL, internal pull-up.
Reference Divider bit 0, VCXO PLL, internal pull-up.
Reference Divider bit 1, VCXO PLL, internal pull-up.
Reference clock input, 5 V tolerant input
Clear input, allows VCXO to free-run when low, internal pull-up.
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
Ground connection for internal digital circuitry.
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
VCXO PLL phase detector Reference Clock output.
Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
IDT™
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
3
MK2069-04
REV H 122109
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
Pin
Number
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Pin
Name
VCLK
VDDP
TCLK
LD
VDD
OER
OEV
OET
OEL
RV2
RV3
RV4
SV0
SV1
RPV
Pin
Type
Output
Power
Output
Output
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pin Description
Clock output from VCXO PLL
Power Supply for output drivers (VCLK, TCLK, RCLK, LD, LDR).
Clock output from Translator PLL
Lock detector output.
Power Supply connection for internal digital circuitry.
Output enable for RCLK. RCLK is tri-stated when low, internal pull-up.
Output enable for VCLK. VCLK is tri-stated when low, internal pull-up.
Output enable for TCLK. TCLK is tri-stated when low, internal pull-up.
Output enable for LD. LD is tri-stated when low, internal pull-up.
Reference Divider bit 2 input, VCXO PLL, internal pull-up.
Reference Divider bit 3 input, VCXO PLL, internal pull-up.
Reference Divider bit 4 input, VCXO PLL, internal pull-up.
Scaler Divider bit 0 input, VCXO PLL, internal pull-up.
Scaler Divider bit 1 input, VCXO PLL, internal pull-up.
RPV divider, VCXO PLL, internal pull-up.
Functional Description
The MK2069-04 is a PLL (Phase Locked Loop) based clock
generator that generates output clocks synchronized to an
input reference clock. It contains two cascaded PLL’s with
user selectable divider ratios.
The first PLL is VCXO-based and uses an external pullable
crystal as part of the normal “VCO” (voltage controlled
oscillator) function of the PLL. The use of a VCXO assures
a low phase noise clock source even when a low PLL loop
bandwidth is implemented. A low loop bandwidth is needed
when the input reference frequency at the phase detector is
low, or when jitter attenuation of the input reference is
desired.
The second PLL is used to translate or multiply the
frequency of the VCXO PLL which has a maximum output
frequency of 27 MHz. This second PLL, or Translator PLL,
uses an on-chip VCO circuit that can provide an output clock
up to 160 MHz. The Translator PLL uses a high loop
bandwidth (typically greater than 1 MHz) to assure stability
of the clock output generated by the VCO. It requires a
stable, high frequency input reference which is provided by
the VCXO.
The divide values of the divider blocks within both PLLs are
set by device pin configuration. This enables the system
designer to define the following:
•
•
•
•
•
Input clock frequency
VCXO crystal frequency
VCLK output frequency
RCLK output frequency, which is also the phase detector
frequency of the VCXO PLL.
TCLK output frequency
Any unused clock or logic outputs can be tri-stated to reduce
interference (jitter, phase noise) on other clock outputs.
Outputs can also be tri-stated for system testing purposes.
External components are used to configure the VCXO PLL
loop response. This serves to maximize loop stability and to
achieve the desired input clock jitter attenuation
characteristics.
IDT™
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
4
MK2069-04
REV H 122109
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
Application Information
The MK2069-04 is a mixed analog / digital integrated circuit
that is sensitive to PCB (printed circuit board) layout and
external component selection. Used properly, the device will
provide the same high performance expected from a
canned VCXO-based hybrid timing device, but at a lower
cost. To help avoid unexpected problems, the guidance
provided in the sections below should be followed.
Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the
following relationship:
FV Divider
f(VCLK) = -------------------------------------------------------------------
×
f(ICLK)
RPV Divider
×
RV Divider
Where:
FV Divider = 1 to 4096
RPV Divider = 1 or 8
RV Divider = 2 to 4097
Because the RPV divider inherently has a higher speed of
operation than the RV divider, the RPV divider should be set
to 8 when this factor is included in the RPV x RV divisor
combination.
VCLK output frequency range is set by the allowable
frequency range of the external VCXO crystal and by the
internal VCXO divider selections:
f(VCLK)
f
(
VCXO
)
=
----------------------
-
SV Divider
Where:
F(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
A higher crystal frequency will generally produce lower
phase noise and therefore is preferred. A crystal frequency
between 13.5 MHz and 27 MHz is recommended.
Because VCLK is generated by the external crystal, the
tracking range of VCLK in a given configuration is limited by
IDT™
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
5
MK2069-04
REV H 122109
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