Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66F(L)FP-xx Series
11
DESCRIPTION
The Hynix HY5V66F(L)FP-xx series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory appli-
cations which require wide data I/O and high bandwidth. HY5V66F(L)F(P)-xxI is organized as 4banks of 1,048,576 x
16.
HY5V66F(L)FP-xx series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
•
•
•
•
•
•
•
•
Voltage: VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
54 Ball FBGA (Lead Free Package)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM, LDQM
•
Internal four banks operation
Auto refresh and self refresh
4096 Refresh cycles / 64ms
- 0
o
C
to 70
o
C
: HY5V66F(L)FP-xx Series
- -40
o
C
to 85
o
C
: HY5V66F(L)FP-xxI Series
Operation Temperature
•
•
•
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency; 2 or 3 Clocks
Burst Read Single Write operation
ORDERING INFORMATION
Part Number
HY5V66F(L)FP-5
HY5V66F(L)FP-6
HY5V66F(L)FP-7
HY5V66F(L)FP-H
HY5V66F(L)FP-5I
HY5V66F(L)FP-6I
HY5V66F(L)FP-7I
HY5V66F(L)FP-HI
Clock
Frequency
200MHz
166MHz
143MHz
133MHz
200MHz
166MHz
143MHz
133MHz
4Banks x 1Mbits x16
LVTTL
0
o
C
to 70
54Ball FBGA
(Lead Free)
Organization
Interface
Operation
Temp.
Package
-40
o
C
to 85
Rev. 1.0 / Apr. 2007
2
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66F(L)FP-xx Series
11
BALL DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
Clock: The system clock input. All other inputs are registered to the SDRAM on the rising
edge of CLK
Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among (deep) power down, suspend or self refresh
Chip Select: Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Bank Address: Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
Command Inputs: RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask: Controls output buffers in read mode and masks input data in write mode
Data Input / Output: Multiplexed data input / output pin
Power supply
I/O Power supply
No connection : These pads should be left unconnected
CLK
INPUT
CKE
INPUT
CS
INPUT
BA0, BA1
INPUT
A0 ~ A11
INPUT
RAS, CAS, WE
INPUT
UDQM, LDQM
DQ0 ~ DQ15
V
DD
/ V
SS
V
DDQ
/ V
SSQ
NC
INPUT
I/O
SUPPLY
SUPPLY
-
Rev. 1.0 / Apr. 2007
4
测试/测量
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