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HYMD5127268-L: 产品描述DDR DRAM Module, 128MX72, 0.8ns, CMOS, 5.250 X 1.250 X 0.150 INCH, DIMM-184; 产品类别存储存储; 文件大小249KB，共16页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HYMD5127268-L概述

DDR DRAM Module, 128MX72, 0.8ns, CMOS, 5.250 X 1.250 X 0.150 INCH, DIMM-184

HYMD5127268-L规格参数

参数名称	属性值
厂商名称	SK Hynix(海力士)
零件包装代码	DIMM
包装说明	DIMM, DIMM184
针数	184
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	DUAL BANK PAGE BURST
最长访问时间	0.8 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	125 MHz
I/O 类型	COMMON
JESD-30 代码	R-XDMA-N184
内存密度	9663676416 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	72
功能数量	1
端口数量	1
端子数量	184
字数	134217728 words
字数代码	128000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	128MX72
输出特性	3-STATE
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装等效代码	DIMM184
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
电源	2.5 V
认证状态	Not Qualified
刷新周期	8192
自我刷新	YES
最大待机电流	0.18 A
最大压摆率	3.51 mA
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.3 V
标称供电电压 (Vsup)	2.5 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子节距	1.27 mm
端子位置	DUAL

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128Mx72 bits

Unbuffered DDR SDRAM DIMM

HYMD512726(L)8-K/H/L

DESCRIPTION

Preliminary

Hynix HYMD512726(L)8-K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Mem-

ory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMD512726(L)8-K/H/L

series consists of eighteen 64Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.

Hynix HYMD512726(L)8-K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry

standard. It is suitable for easy interchange and addition.

Hynix HYMD512726(L)8-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous opera-

tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are

latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising

and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All

input and output voltage levels are compatible with SSTL_2. High s1peed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD512726(L)8-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

1GB (128M x 72) Unbuffered DDR DIMM based on

64Mx8 DDR SDRAM

JEDEC Standard 184-pin dual in-line memory mod-

ule (DIMM)

Error Check Correction (ECC) Capability

2.5V +/- 0.2V VDD and VDDQ Power supply

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

•

Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

Data inputs on DQS centers when write (centered

DQ)

Data strobes synchronized with output data for read

and input data for write

Programmable CAS Latency 1.5 / 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

tRAS Lock-out function supported

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192refresh cycles / 64ms

ORDERING INFORMATION

Part No.

HYMD512726(L)8-K

HYMD512726(L)8-H

HYMD512726(L)8-L

=2.5V

DDQ

=2.5V

Power Supply

Clock Frequency

133MHz (*DDR266A)

133MHz (*DDR266B)

125MHz (*DDR200)

Interface

Form Factor

184pin Unbuffered DIMM

5.25 x 1.25 x 0.15 inch

SSTL_2

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2/Jul. 02

HYMD5127268-L相似产品对比

	HYMD5127268-L	HYMD512726L8-K	HYMD5127268-K	HYMD5127268-H	HYMD512726L8-H	HYMD512726L8-L
描述	DDR DRAM Module, 128MX72, 0.8ns, CMOS, 5.250 X 1.250 X 0.150 INCH, DIMM-184	DDR DRAM Module, 128MX72, 0.75ns, CMOS, 5.250 X 1.250 X 0.150 INCH, DIMM-184	DDR DRAM Module, 128MX72, 0.75ns, CMOS, 5.250 X 1.250 X 0.150 INCH, DIMM-184	DDR DRAM Module, 128MX72, 0.75ns, CMOS, 5.250 X 1.250 X 0.150 INCH, DIMM-184	DDR DRAM Module, 128MX72, 0.75ns, CMOS, 5.250 X 1.250 X 0.150 INCH, DIMM-184	DDR DRAM Module, 128MX72, 0.8ns, CMOS, 5.250 X 1.250 X 0.150 INCH, DIMM-184
厂商名称	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
包装说明	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184
针数	184	184	184	184	184	184
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
最长访问时间	0.8 ns	0.75 ns	0.75 ns	0.75 ns	0.75 ns	0.8 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	125 MHz	133 MHz	133 MHz	133 MHz	133 MHz	125 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184
内存密度	9663676416 bit	9663676416 bit	9663676416 bit	9663676416 bit	9663676416 bit	9663676416 bit
内存集成电路类型	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
内存宽度	72	72	72	72	72	72
功能数量	1	1	1	1	1	1
端口数量	1	1	1	1	1	1
端子数量	184	184	184	184	184	184
字数	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words
字数代码	128000000	128000000	128000000	128000000	128000000	128000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	128MX72	128MX72	128MX72	128MX72	128MX72	128MX72
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
封装等效代码	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
电源	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192	8192	8192
自我刷新	YES	YES	YES	YES	YES	YES
最大待机电流	0.18 A	0.18 A	0.18 A	0.18 A	0.18 A	0.18 A
最大压摆率	3.51 mA	3.78 mA	3.78 mA	3.78 mA	3.78 mA	3.51 mA
最大供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
最小供电电压 (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	NO	NO	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
端子节距	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL

HYMD5127268-L

HYMD5127268-L概述

HYMD5127268-L规格参数

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