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SN74LS138
1−of−8 Decoder/
Demultiplexer
The LSTTL/MSI SN74LS138 is a high speed 1-of-8 Decoder/
Demultiplexer. This device is ideally suited for high speed bipolar
memory chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just three LS138
devices or to a 1-of-32 decoder using four LS138s and one inverter.
The LS138 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
•
Demultiplexing Capability
•
Multiple Input Enable for Easy Expansion
•
Typical Power Dissipation of 32 mW
•
Active Low Mutually Exclusive Outputs
•
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current
−
High
Output Current
−
Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
−0.4
8.0
Unit
V
°C
mA
mA
16
1
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LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
SOIC
D SUFFIX
CASE 751B
16
1
SOEIAJ
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
SN74LS138N
SN74LS138D
SN74LS138DR2
SN74LS138M
SN74LS138MEL
Package
16 Pin DIP
SOIC−16
SOIC−16
SOEIAJ−16
SOEIAJ−16
Shipping
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
See Note 1
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 8
1
Publication Order Number:
SN74LS138/D
SN74LS138
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
O
0
15
O
1
14
O
2
13
O
3
12
O
4
11
O
5
10
O
6
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
A
0
2
A
1
3
A
2
4
E
1
5
E
2
6
E
3
7
O
7
8
GND
LOADING
(Note a)
PIN NAMES
A
0
− A
2
E
1
, E
2
E
3
O
0
− O
7
Address Inputs
Enable (Active LOW) Inputs
Enable (Active HIGH) Input
Active LOW Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA
HIGH/1.6 mA LOW.
LOGIC SYMBOL
1 2 3
456
1 23
A
0
A
1
A
2
E
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
15 14 13 12 11 10 9 7
V
CC
= PIN 16
GND = PIN 8
LOGIC DIAGRAM
A
2
3
2
A
1
1
A
0
4
E
1
E
2
E
3
5
6
V
CC
= PIN 16
GND = PIN 8
= Pin Numbers
7
9
10
11
12
13
14
15
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
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2
SN74LS138
FUNCTIONAL DESCRIPTION
The LS138 is a high speed 1-of-8 Decoder/Demultiplexer
fabricated with the low power Schottky barrier diode
process. The decoder accepts three binary weighted inputs
(A
0
, A
1
, A
2
) and when enabled provides eight mutually
exclusive active LOW Outputs (O
0
−O
7
). The LS138
features three Enable inputs, two active LOW (E
1
, E
2
) and
one active HIGH (E
3
). All outputs will be HIGH unless E
1
and E
2
are LOW and E
3
is HIGH. This multiple enable
function allows easy parallel expansion of the device to a
1-of-32 (5 lines to 32 lines) decoder with just four LS138s
and one inverter. (See Figure a.)
The LS138 can be used as an 8-output demultiplexer by
using one of the active LOW Enable inputs as the data input
and the other Enable inputs as strobes. The Enable inputs
which are not used must be permanently tied to their
appropriate active HIGH or active LOW state.
TRUTH TABLE
INPUTS
E
1
H
X
X
L
L
L
L
L
L
L
L
E
2
X
H
X
L
L
L
L
L
L
L
L
E
3
X
X
L
H
H
H
H
H
H
H
H
A
0
X
X
X
L
H
L
H
L
H
L
H
A
1
X
X
X
L
L
H
H
L
L
H
H
A
2
X
X
X
L
L
L
L
H
H
H
H
O
0
H
H
H
L
H
H
H
H
H
H
H
O
1
H
H
H
H
L
H
H
H
H
H
H
O
2
H
H
H
H
H
L
H
H
H
H
H
OUTPUTS
O
3
H
H
H
H
H
H
L
H
H
H
H
O
4
H
H
H
H
H
H
H
L
H
H
H
O
5
H
H
H
H
H
H
H
H
L
H
H
O
6
H
H
H
H
H
H
H
H
H
L
H
O
7
H
H
H
H
H
H
H
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
A
0
A
1
A
2
LS04
A
3
A
4
H
123
A
0
A
1
A
2
E
A
0
A
1
A
2
LS138
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
123
E
A
0
A
1
A
2
LS138
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
123
E
A
0
A
1
A
2
LS138
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
31
123
E
LS138
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
0
Figure a
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3
SN74LS138
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
V
OL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
−0.65
3.5
0.25
0.35
0.4
0.5
20
0.1
−0.4
−20
−100
10
Min
2.0
0.8
−1.5
Typ
Max
Unit
V
V
V
V
V
V
μA
mA
mA
mA
mA
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
=
−
18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
I
OL
= 8.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
Output LOW Voltage
I
IH
I
IL
I
OS
I
CC
Input HIGH Current
Input LOW Current
Short Circuit Current (Note 2)
Power Supply Current
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25°C)
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Propagation Delay
Address to Output
Propagation Delay
Address to Output
Propagation Delay E
1
or E
2
Enable to Output
Propagation Delay E
3
Enable to Output
Levels of
Delay
2
2
3
3
2
2
3
3
Limits
Min
Typ
13
27
18
26
12
21
17
25
Max
20
41
27
39
18
32
26
38
Unit
ns
ns
ns
ns
Test Conditions
V
CC
= 5.0 V
C
L
= 15 pF
AC WAVEFORMS
1.3 V
t
PHL
V
OUT
1.3 V
1.3 V
t
PLH
1.3 V
V
OUT
V
IN
1.3 V
t
PHL
1.3 V
t
PLH
1.3 V
1.3 V
V
IN
Figure 1.
Figure 2.
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