HB52E649E12-A6B/B6B
512 MB Registered SDRAM DIMM
64-Mword
×
72-bit, 100 MHz Memory Bus, 1-Bank Module
(18 pcs of 64 M
×
4 Components)
PC100 SDRAM
ADE-203-1088 (Z)
Preliminary
Rev. 0.0
Jul. 14, 1999
Description
The HB52E649E12 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed
as an optimized main memory solution for 8-byte processor applications. The HB52E649E12 is a 64M
×
72
×
1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM
(HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1
piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52E649E12 is 168-pin sock-
et type package (dual lead out). Therefore, the HB52E649E12 makes high density mounting possible without
surface mount technology. The HB52E649E12 provides common data inputs and outputs. Decoupling ca-
pacitors are mounted beside each TSOP on the module board.
Features
•
•
Fully compatible with: JEDEC standard outline 8-byte DIMM
—
: Intel PCB Reference design (Rev.1.2)
168-pin socket type package (dual lead out)
— Outline: 133.37 mm (Length)
×
43.18 mm (Height)
×
4.00 mm (Thickness)
— Lead pitch: 1.27 mm
3.3 V power supply
Clock frequency: 100 MHz (max)
LVTTL interface
Data bus width:
×
72 ECC
Single pulsed RAS
4 Banks can operates simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
— Sequential
— Interleave
: 3/4 (HB52E649E12-A6B)
Programmable CE latency
_
: 4 (HB52E649E12-B6B)
•
•
•
•
•
•
•
•
•
•
HB52E649E12-A6B/B6B
•
•
•
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
— Auto refresh
— Self refresh
Ordering Information
Type No.
HB52E649E12-A6B
HB52E649E12-B6B
Frequency
100 Mhz
100 Mhz
CE latency Package
3/4
4
Contact pad
168-pin dual lead out socket type Gold
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Pin name
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
CB1
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin name
V
SS
NC
S2
DQMB2
DQMB3
NC
V
CC
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
CC
DQ20
NC
NC
NC
V
SS
Pin No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Pin name
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
CB4
CB5
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Pin name
V
SS
CKE0
NC
DQMB6
DQMB7
NC
V
CC
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
CC
DQ52
NC
NC
REGE
V
SS
2
HB52E649E12-A6B/B6B
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin name
V
SS
NC
NC
V
CC
W
DQMB0
DQMB1
S0
NC
V
SS
A0
A2
A4
A6
A8
A10 (AP)
BA1
V
CC
V
CC
CK0
Pin No.
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin name
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
CC
Pin No.
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin name
V
SS
NC
NC
V
CC
CE
DQMB4
DQMB5
NC
RE
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
CC
CK1
A12
Pin No.
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin name
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
CC
Pin Description
Pin name
A0 to\~A12
Function
Address input
— Row addressA0 to A12
— Column addressA0 to A9, A11
BA0/BA1
DQ0 to DQ63
CB0 to CB7
S0, S2
RE
CE
W
DQMB0 to DQMB7
CK0 to CK3
CKE0
WP
REGE*
SDA
SCL
SA0 to SA2
1
Bank select address
Data input/output
Check bit (Data input/output)
Chip select input
Row enable (RAS) input
Column enable (CAS) input
Write enable input
Byte data mask
Clock input
Clock enable input
Write protect for serial PD
Register enable
Data input/output for serial PD
Clock input for serial PD
Serial address input
3
HB52E649E12-A6B/B6B
Pin name
V
CC
V
SS
NC
Function
Primary positive power supply
Ground
No connection
Note: 1. REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high state
(“registerd” mode).
Serial PD Matrix*
1
Byte
No.
0
1
2
3
4
5
6
7
8
9
Function described
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Number of row addresses bits
Number of column addresses
bits
Number of banks
Module data width
Module data width (continued)
Module interface signal levels
SDRAM cycle time
(highest CE latency)
10 ns
SDRAM access from Clock
(highest CE latency)
6 ns
Module configuration type
Refresh rate/type
Bit Bit Bit Bit Bit Bit Bit Bit Hex val-
7
6
5
4
3
2
1
0
ue
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
80
08
04
0D
0B
01
48
00
01
A0
Comments
128
256 byte
SDRAM
13
11
1
72 bit
0 (+)
LVTTL
CL = 3
10
0
1
1
0
0
0
0
0
60
*
7
11
12
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
02
82
ECC
Normal
(7.8125
µµs)
Self refresh
64M
×
4
×
4
1 CLK
13
14
15
SDRAM width
Error checking SDRAM width
SDRAM device attributes:
minimum clock delay for back-
to-back random column
addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes:
number of banks on SDRAM
device
SDRAM device attributes:
CE latency
(-A6B)
(-B6B)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
04
04
01
16
17
0
0
0
0
0
0
0
0
1
0
1
1
1
0
1
0
0F
04
1, 2, 4, 8
4
18
0
0
0
0
0
1
1
0
06
2/3
0
0
0
0
0
1
0
0
04
3
4
HB52E649E12-A6B/B6B
Byte
No.
19
20
21
22
23
Function described
SDRAM device attributes:
S latency
SDRAM device attributes:
W latency
SDRAM device attributes
SDRAM device attributes:
General
SDRAM cycle time
(2nd highest CE latency)
(-A6B) 10 ns
(-B6B) Undefined
24
SDRAM access from Clock
(2nd highest CE latency)
(-A6B) 6 ns
(-B6B) Undefined
25
SDRAM cycle time
(3rd highest CE latency)
Undefined
SDRAM access from Clock
(3rd highest CE latency)
Undefined
Minimum row precharge time
Row active to row active min
RE to CE delay min
Minimum RE pulse width
Bit Bit Bit Bit Bit Bit Bit Bit Hex val-
7
6
5
4
3
2
1
0
ue
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
0
0
01
01
16
0E
A0
Comments
0
0
Registered
V
CC
±
10%
CL = 2
*
7
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
00
60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
26
0
0
0
0
0
0
0
0
00
27
28
29
30
31
32
33
34
35
62
63
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
×
1
1
0
0
1
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
×
0
0
1
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
0
0
×
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
×
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
×
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
1
0
×
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
×
0
0
1
0
1
14
14
14
32
80
20
10
20
10
00
12
1A
18
07
00
××
48
42
35
32
45
20 ns
20 ns
20 ns
50 ns
1 bank
512M byte
2 ns*
7
1 ns*
7
2 ns*
7
1 ns*
7
Future use
Rev. 1.2A
26
24
HITACHI
*
3
(ASCII-
8bit code)
H
B
5
2
E
5
Density of each bank on module 1
Address and command signal
input setup time
Address and command signal
input hold time
Data signal input setup time
Data signal input hold time
SPD data revision code
Checksum for bytes 0 to 62
(-A6B)
(-B6B)
0
0
0
0
0
0
0
0
36 to 61 Superset information
64
72
73
74
75
76
77
Manufacturer’s JEDEC ID code 0
Manufacturing location
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
×
0
0
0
0
0
65 to 71 Manufacturer’s JEDEC ID code 0
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