HB52F649E1-75B
512 MB Registered SDRAM DIMM
64-Mword
×
72-bit, 133 MHz Memory Bus, 1-Bank Module
(18 pcs of 64 M
×
4 Components)
PC133SDRAM
ADE-203-1080 (Z)
Preliminary
Rev. 0.0
Jun. 28, 1999
Description
The HB52F649E1 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed
as an optimized main memory solution for 8-byte processor applications. The HB52F649E1 is a 64M
×
72
×
1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM
(HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 3 pieces of register driver and 1
piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52F649E1 is 168-pin socket
type package (dual lead out). Therefore, the HB52F649E1 makes high density mounting possible without
surface mount technology. The HB52F649E1 provides common data inputs and outputs. Decoupling
capacitors are mounted beside each TSOP on the module board.
Features
•
Fully compatible with : JEDEC standard outline 8-byte DIMM
•
168-pin socket type package (dual lead out)
Outline: 133.35 mm (Length)
×
43.18 mm (Height)
×
4.00 mm (Thickness)
Lead pitch: 1.27 mm
•
3.3 V power supply
•
Clock frequency: 133 MHz (max)
•
LVTTL interface
•
Data bus width:
×
72 ECC
•
Single pulsed
RAS
•
4 Banks can operates simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length: 1/2/4/8
Preliminary: The Specifications of this device are subject to change without notice. Please contact to your nearest
Hitachi’s sales Dept. regarding specifications.
HB52F649E1-75B
•
2 variations of burst sequence
Sequential
Interleave
•
Programmable
CE
latency : 4
•
Byte control by DQMB
•
Refresh cycles: 8192 refresh cycles/64 ms
•
2 variations of refresh
Auto refresh
Self refresh
Ordering Information
Type No.
HB52F649E1-75B
Frequency
133 MHz
CE
latency
4
Package
Contact pad
168-pin dual lead out socket type Gold
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
2
HB52F649E1-75B
Pin No.
36
37
38
39
40
41
42
Pin name
A6
A8
A10 (AP)
BA1
V
CC
V
CC
CK0
Pin No.
78
79
80
81
82
83
84
Pin name
V
SS
CK2
NC
WP
SDA
SCL
V
CC
Pin No.
120
121
122
123
124
125
126
Pin name
A7
A9
BA0
A11
V
CC
CK1
A12
Pin No.
162
163
164
165
166
167
168
Pin name
V
SS
CK3
NC
SA0
SA1
SA2
V
CC
Pin Description
Pin name
A0 to A12
Function
Address input
Row address
Column address
BA0/BA1
DQ0 to DQ63
CB0 to CB7
S0, S2
RE
CE
W
DQMB0 to DQMB7
CK0 to CK3
CKE0
WP
REGE*
1
SDA
SCL
SA0 to SA2
V
CC
V
SS
NC
Note:
Bank select address
Data input/output
Check bit (Data input/output)
Chip select input
Row enable (RAS) input
Column enable (CAS) input
Write enable input
Byte data mask
Clock input
Clock enable input
Write protect for serial PD
Register enable
Data input/output for serial PD
Clock input for serial PD
Serial address input
Primary positive power supply
Ground
No connection
1. REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high state
(“registerd” mode).
A0 to A12
A0 to A9, A11
4
HB52F649E1-75B
Serial PD Matrix*
1
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Number of row addresses bits
Number of column addresses
bits
Number of banks
Module data width
Module data width (continued)
Module interface signal levels
SDRAM cycle time
(highest
CE
latency)
7.5 ns
SDRAM access from Clock
(highest
CE
latency)
5.4 ns
Module configuration type
Refresh rate/type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
80
08
04
0D
0B
01
48
00
01
75
128
256 byte
SDRAM
13
11
1
72 bit
0 (+)
LVTTL
CL = 3
10
0
1
0
1
0
1
0
0
54
*
5
11
12
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
02
82
ECC
Normal
(7.8125
µs)
Self refresh
64M
×
4
×
4
1 CLK
13
14
15
SDRAM width
Error checking SDRAM width
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
04
04
01
SDRAM device attributes:
0
minimum clock delay for back-to-
back random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes:
number of banks on SDRAM
device
SDRAM device attributes:
CE
latency
SDRAM device attributes:
S
latency
SDRAM device attributes:
W
latency
SDRAM device attributes
0
0
16
17
0
0
0
0
0
0
1
0
1
1
1
0
1
0
0F
04
1, 2, 4, 8
4
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
06
01
01
16
2/3
0
0
Registered
5
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