EEPROM Programmable PLL Die for
LVCMOS Crystal Oscillator
IDT5V7855
DATA SHEET
General Description
The IDT5V7855 is a programmable PLL-based clock generator used
for crystal oscillator modules. The device incorporates an on-chip
crystal oscillator with a programmable capacitor tuning array to
support direct connection with fundamental-mode crystals between
16MHz – 50MHz. The capacitor tuning array offers a total of 9 bits of
resolution and provides a step of 0.01pF.
The device incorporates on-chip non-volatile EEPROM cells which
can store all the device settings and maintain them even when there
is no power. The serial programming interface is implemented with
dual-use pins for the clock and data. The CONT input can be
programmed as either a power down input or an output enable input.
Crystal oscillator modules using this device can be stocked as blank
parts and custom frequencies programmed in package at the last
stage before shipping. This enables fast-turn manufacture of custom
and standard crystal oscillators without the need for expensive
dedicated crystals.
The IDT PLL uses a patent-pending fractional multiplier technique to
provide ultra-high resolution multiplication and division from input to
output with low jitter. In addition, prescaler and post-
divider circuits are included to enhance the granularity of clock
scaling. The PLL may also be bypassed in order to operate the
device as a non-PLL fundamental-mode crystal oscillator for
applications that do not require frequency multiplication. The device
is fabricated using advance technology and can support both 2.5V
and 3.3V operation. The device is small enough to fit into
small-footprint crystal oscillators. This is the industry’s smallest
programmable die and can support crystal oscillator packages as
small as 20mm x 16mm.
Features
•
•
•
Input: 16MHz – 50MHz fundamental mode crystal
Output frequency range: 1MHz – 170MHz in PLL mode,
1MHz – 50MHz in non-PLL mode
On-chip EEPROM to store device configuration
– 19-bit high-resolution fractional programmable multiplier
– 3-bit prescaler
– 7-bit output divider
– 9-bit crystal oscillator tuning capacitor array
– Selectable function power down or OE control pin
In-package serial programming interface through dual-use pins
Full 2.5V and 3.3V operating supply
Maximum frequency shift across supply voltage: ±1ppm
Available in die pack, lead-free RoHS compliant
ESD Human Body Model (HBM) and Machine Model (MM):
– HBM: 2000V
– MM: 200V
Small die size: 0.75mm x 0.75mm
Supports 20mm x 16mm package size
-40°C to 85°C ambient operating temperature
•
•
•
•
•
•
•
•
Functional Block Diagram
xg
x2
0
Pad Assignment
V
DD
1
OSC
xd
Pre-Scaler
3-bit
PFD
VCO
1
Output
Divider
÷2
OUT
V
DD
2
xd 3
8 OUT
Tuning
Cap
9-bit
Fractional
Multiplier
19-bit
7-bit
xg 4
CONT 5
6
V
SS
7 V
SS
EEPROM
CONT
Pullup
IDT5V7855
0.75mm x 0.75mm Die
IDT5V7855-DPK REVISION A MARCH 11, 2010
1
©2010 Integrated Device Technology, Inc.
IDT5V7855 Data Sheet
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR
Table 1. Pad Descriptions
Number
1, 2
3, 4
5
6, 7
8
Name
V
DD
xd, xg
CONT
V
SS
OUT
Input
Input
Power
I/O
Pullup
Type
Power
Description
Power supply pins. Both pads must be bonded.
Crystal oscillator interface. xg is the input. xd is the output.
Programmable to function as power down or output enable. Serves as VPP and data
input during programming mode.
Power supply ground. Only one pad should be bonded. Either pad can be used to
accommodate optimal bond wire placement
Single-ended clock output. Serves as clock input during programming mode.
NOTE:
Pullup
refers to internal input resistor.
Table 2. Pad Characteristics
Symbol
R
PULLUP
R
OUT
Parameter
Input Pullup Resistor
Output Impedance
V
DD
= 3.3V
V
DD
= 2.5V
Test Conditions
Minimum
Typical
51
25
37
Maximum
Units
k
Ω
Ω
Ω
IDT5V7855-DPK REVISION A MARCH 11, 2010
2
©2010 Integrated Device Technology, Inc.
IDT5V7855 Data Sheet
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR
Functional Description
The output frequency of the IDT5V7855 is determined by the crystal
frequency and the three programmable divider/multiplier registers:
Prescaler (P), Fractional Multiplier (M), and Output Divider (D). The
prescaler (P) is a 3-bit integer register while the output divider (D) is
a 7-bit integer register. The fractional multiplier (M) is a 19-bit register
and has the feature of a fractional component in addition to the
integer value. This allows the IDT5V7855 to be programmed to a
wide variety of output frequencies from a single input crystal
frequency.
Table 3A. Prescaler Table
Crystal Range
(MHz)
16 – 50
16 – 50
16 – 50
21.25 – 50
26.5625 – 50
31.875 – 50
37.1875 – 50
Prescaler
(P)
1
2
3
4
5
6
7
Phase Detector Frequency
(MHz)
16 – 50
8 – 25
5.3333 – 16.6667
5.3125 – 12.5
5.3125 – 10
5.3125 – 8.3333
5.3125 – 7.1429
Figure 1. Simplified Block Diagram
The actual values which may be programmed into the various
registers depend on the specified operational ranges of some of the
PLL components such as the VCO and crystal oscillator. As shown
in tables 5 and 6A, these ranges are:
VCO Range:
170MHz to 340MHz
XTAL Oscillator Range:
16MHz to 50MHz
The minimum value permitted for the feedback register is a function
of the minimum VCO frequency and the maximum phase detector
reference frequency. The maximum phase detector reference
frequency is set by the maximum crystal frequency (50MHz) divided
by the minimum prescaler divider (1) and is therefore 50MHz. The
feedback fractional multiplier register operational range can be
determined as:
M Min:
170MHz ÷ 50MHz = 3.4
M Max:
31.9993896
≈
32
The maximum value that can be programmed into the fractional
multiplier (all 19 bits “1”) is approximately 32 (actual value is
31.99993896).
Given the VCO range and the feedback divider range, the minimum
phase detector frequency can be determined from the minimum VCO
frequency and the maximum feedback divider as:
Phase Detector Min:
170MHz ÷ 32 = 5.3125MHz
Phase Detector Max:
50MHz
The maximum value is set by the specified maximum crystal
frequency.
Fractional Multiplier (M)
The Fractional Multiplier (M) is a 19-bit register. The operational
range of the fractional multiplier is 3.4 to approximately 32 (actually
31.99993896). The decimal multiplier value obtained from the 19-bit
fractional multiplier register can be determined as:
M
BIN
-
M
DEC
= ---------------
16384
M
DEC
is the fractional multiplier (decimal) value
M
BIN
is the value programmed in the 19-bit register
The fractional portion of the fractional multiplier allows a
programming frequency resolution to 61/M
DEC
ppm. Note that higher
M
DEC
values will produce lower ppm error.
Examples:
For a fractional multiplier register M
BIN
of
1010101000000000000 binary
348160
M
DEC
= ------------------- = 21.2500
-
16384
The ppm resolution (single LSB bit change in the M
BIN
) for this setting
is:
61ppm
------------------ = 2.9ppm
-
21.25
For a fractional multiplier register M
BIN
of
0010101010000000000 binary
87040
-
M
DEC
= --------------- = 5.3125
16384
The ppm resolution (single LSB bit change in the M
BIN
) for this setting
is:
61ppm
------------------ = 11.5ppm
-
5.3125
Prescaler (P)
The Prescaler (P) divides down the input crystal frequency prior to
the internal phase detector. The prescaler register is a 3-bit register
so the possible values which may be programmed are 1 through 7.
The specified input crystal frequency range is: 16MHz to 50MHz and
the phase detector range is: 5.3125MHz to 50MHz. So the possible
settings and ranges are:
IDT5V7855-DPK REVISION A MARCH 11, 2010
3
©2010 Integrated Device Technology, Inc.
IDT5V7855 Data Sheet
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR
Output Divider (D)
The Output Divider register is a 7-bit register so the possible values
which may be programmed are 1 through 127. Combining the
information from the three registers, including the final output divider
and the crystal frequency, the output frequency may be derived.
The actual frequency produced from a given crystal frequency may
be determined as:
MDEC
-
FOUT =
(
FXTAL
)
x --------------------------
P x
(
D x 2
)
F
OUT
F
XTAL
P
D
M
DEC
is the output frequency
is the Crystal Frequency
is the Prescaler Value
is the Output Divider Value
is the Fractional Divider (decimal) Value
Crystal Range
(MHz)
16 – 50
16 – 50
16 – 50
21.25 – 50
26.5625 – 50
Using table 3B, identify the crystal frequency from the given ranges
and select the associated prescaler (P) value. The phase detector
frequency is then calculated as:
F
XTAL
-
F
PHASE
–
DET
=
---------------
P
Table 3B. Crystal Range Table
Prescaler (P)
1
2
3
4
5
6
Phase Detector
Frequency (MHz)
16 – 50
8 – 25
5.3333 – 16.6667
5.3125 – 12.5
5.3125 – 10
5.3125 – 8.3333
Fine Frequency Adjustment
The IDT5V7855 also has a fine frequency adjustment capability
utilizing adjustable tuning capacitors in the crystal oscillator. These
capacitors are set through a tuning capacitor register which is a 9-bit
register and the resolution of the tuning capacitance is approximately
0.01pF per bit. The frequency ppm tuning performance can be found
by:
C1
1
1
-
FREQ
(
ppm
)
= ------- x
-----------------------------------------------------------------
–
---------------------
x10 6 ppm
-
-
2 C0 + CL + C
STEP
x T
REG
C0 + CL
C1
C0
CL
C
STEP
T
REG
is the Crystal Motional Capacitance
is the Crystal Shunt Capacitance
is the Inherent (parasitic) Load Capacitance
is the Tuning Capacitance Resolution 0.01pF
is the Tuning Capacitor Register Value from 0 to 511
31.875 – 50
Identify the range(s) that match the desired output frequency and
select the associated Output Divider (D) value. The VCO frequency
is then calculated as:
F
VCO
=
(
F
OUT
x D x 2
)
Table 3C. F
VCO
Table
Output Frequency Range
(MHz) F
OUT
85.0000 – 170.0000
42.5000 – 85.0000
28.3333 – 56.6667
Output Divider
(D)
1
2
3
4
5
6
•••
125
126
127
VCO
Frequency
(MHz)
170 – 340
170 – 340
170 – 340
170 – 340
170 – 340
170 – 340
•••
170 – 340
170 – 340
170 – 340
Determining the Appropriate Register Settings
A typical use for this type of device is generating virtually any
frequency between 1MHz to 170MHz from a single crystal frequency
value. The steps required to accomplish this are:
1.
2.
3.
4.
5.
6.
Determine the crystal frequency.
Determine the desired output frequency.
Determine the proper prescaler value using the crystal
frequency and the associated phase detector frequency.
Determine the proper output divider using the desired
output frequency to optimize the internal VCO frequency.
Determine the appropriate fractional multiplier value using
the phase detector frequency and the VCO frequency.
Determine the M
BIN
value by multiplying the M
DEC
value
by 16384.
21.2500 – 42.5000
17.0000 – 34.0000
14.1667 – 28.3333
•••
0.6800 – 1.3600 (NOTE)
0.6746 – 1.3492 (NOTE)
0.6693 – 1.3386 (NOTE)
NOTE: The specified minimum output frequency is 1MHz. While
output frequencies less than 1MHz are possible, specified device
performance is not guaranteed.
IDT5V7855-DPK REVISION A MARCH 11, 2010
4
©2010 Integrated Device Technology, Inc.
IDT5V7855 Data Sheet
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR
The fractional multiplier is determined from the phase detector
frequency and the VCO frequency using the following equations.
Calculate the fractional multiplier decimal value:
F
VCO
M
DEC
= -----------------------------------
F
PHASE
–
DET
Calculate the fractional multiplier register binary value:
M
BIN
= M
DEC
x 16384
Example 1:
The crystal frequency is 27MHz and the desired output frequency is
166.66667MHz.
1.
With a crystal frequency of 27MHz, the appropriate
prescaler value is 1 and the associated phase detector
frequency would be: 27MHz ÷ 1 = 27MHz.
For an output frequency of 166.6667MHz, the output
divider which can be used with a VCO frequency in the proper
170MHz to 340MHz range is 1, and the resulting
VCO frequency is: 166.6667MHz x 1 x 2 = 333.33MHz.
The fractional multiplier is calculated as the VCO frequency
divided by the phase detector frequency or
333.33MHz ÷ 27MHz = 12.345679.
The M
BIN
is found by 12.345679 x 16384 = 202271.6 and is
rounded to 202272.
Due to the rounding, the actual M
DEC
value will be 12.3457
and the actual output frequency will be:
3.
The fractional multiplier is calculated as the VCO frequency
divided by the phase detector frequency. So, for the
possible combinations identified, the resulting fractional
multiplier could be one of nine possibilities.
Table 3D. Fractional Multiplier Table
P=1
F
PHASE_DET
(48MHz)
D=4
M
DEC
=
F
VCO
=
200MHz
D=5
M
DEC
=
F
VCO
=
250MHz
D=6
M
DEC
=
F
VCO
=
300MHz
200MHz
----------------------
-
48MHz
4.16666
250MHz
----------------------
-
48MHz
5.20833
300MHz
----------------------
-
48MHz
6.5
P=2
F
PHASE_DET
(24MHz)
200MHz
-
M
DEC
= ----------------------
24MHz
8.33333
250MHz
M
DEC
= ----------------------
-
24MHz
10.41666
300MHz
-
M
DEC
= ----------------------
24MHz
12.5
P=3
F
PHASE_DET
(16MHz)
200MHz
-
M
DEC
= ----------------------
16MHz
12.5
250MHz
M
DEC
= ----------------------
-
16MHz
15.625
300MHz
-
M
DEC
= ----------------------
16MHz
18.75
2.
3.
4.
4.
5.
M
DEC
12.3457
F
OUT
= F
XTAL
x -------------------------- = 27MHz x --------------------
-
-
P x
(
D x 2
)
1 x1 x 2
F
OUT
= 166.66699MHz
(NOTE: This is an error of only 1.94ppm.)
With the different M
DEC
values to choose from, how does
one select the ‘best’ value? In general, selecting a fractional
value which reduces the ppm error is the first selection
criteria. This applies to M
DEC
values which have the fewest
non-zero decimal places or M
DEC
values which have large
integer values. This criteria would eliminate the
M
DEC
= 4.16666, 5.208333, 8.33333, and 10.4166666
options. After the ppm error selection is made and if there are
still other options, generally the higher VCO frequency will
provide better performance. In this example, the higher VCO
frequency corresponds with D = 6 and the associated P and
M
DEC
values of 1 and 6.25, 2 and 12.5, or 3 and 18.75. Lastly,
the higher phase detector frequency generally provides better
performance. So for this example, the condition of P = 1,
M
DEC
= 6.25, and D = 6 would be the preferred choice.
The M
BIN
is found by: 6.25 x 16384 = 102400. (No rounding is
necessary.)
Verifying the values
M
DEC
12.5
F
OUT
= F
XTAL
x -------------------------- = 48MHz x --------------------
-
-
P x
(
D x 2
)
2 x6 x 2
Example 2:
The starting crystal frequency is 48MHz and the desired output
frequency is 25MHz.
1. With a starting crystal frequency of 48MHz, the appropriate
prescaler value can be either 1, 2 or 3 and the associated
phase detector frequency would be either:
48MHz ÷ 1 = 484MHz,
48MHz ÷ 2 = 24MHz or,
48MHz ÷ 3 = 16MHz.
2.
For an output frequency of 25MHz, the output dividers
which can be used with a VCO frequency in the proper
170MHz to 340MHz range are: 4, 5, or 6, and the resulting
VCO frequencies is: 200MHz, 250MHz, or 300MHz.
5.
6.
IDT5V7855-DPK REVISION A MARCH 11, 2010
5
©2010 Integrated Device Technology, Inc.
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
