SMAJ530 and SMAJ550
Vishay Semiconductors
formerly General Semiconductor
Surface Mount T
RANS
Z
ORB
®
Transient Voltage Suppressors
DO-214AC
(SMA)
0.065 (1.65)
0.049 (1.25)
Cathode Band
Steady State Power
1W
Peak Pulse Power
300W
Reverse Voltage
530,550V
0.110 (2.79)
0.100 (2.54)
Mounting Pad Layout
0.060 MIN
(1.52 MIN)
0.094 MAX
(2.38 MAX)
0.177 (4.50)
Dimensions in inches
and (millimeters)
0.157 (3.99)
0.012 (0.305)
0.006 (0.152)
0.090 (2.29)
0.078 (1.98)
0.050 MIN
(1.27 MIN)
0.220 REF
(5.58)
0.008 (0.203) MAX.
0.208 (5.28)
0.194 (4.93)
0.060 (1.52)
0.030 (0.76)
Mechanical Data
Case:
JEDEC DO-214AC molded plastic body over
passivated chip
Terminals:
Solder plated, solderable per MIL-STD-750,
Method 2026
Polarity:
The band denotes the cathode, which is positive with
respect to the anode under normal TVS operation
Mounting Position:
Any
Weight:
0.002 oz., 0.064 g
Packaging Codes – Options (Antistatic):
51 – 1K per Bulk box, 20K/carton
61 – 1.8K per 7" plastic Reel (12mm tape), 36K/carton
5A – 7.5K per 13" plastic Reel (12mm tape), 75K/carton
T
A
= 25
O
C unless otherwise noted.
Features
• Plastic package has Underwriters Laboratory
Flammability Classification 94V-0
• Protects power IC controllers such as TOPSwitch
®
• Glass passivated junction
• High temperature soldering guaranteed:
250°C/10 seconds at terminals
• Excellent clamping capability
• Available in unidirectional only
Maximum Ratings and Thermal Characteristics
Parameter
Device marking code
Steady state power dissipation
(3)
Peak pulse power dissipation
(1)(2)(5)
(Fig. 1)
Stand-off voltage
Typical thermal resistance junction-to-lead
Typical thermal resistance junction-to-ambient
Operating junction and storage temperature range
P
M(AV)
P
PPM
V
WM
R
θJL
R
θJA
T
J
, T
STG
Symbol
SMAJ530
HD
1.0
SMAJ550
SB
Unit
W
W
Minimum 300
477
27
75
–55 to +150
495
V
°C/W
°C/W
°C
Electrical Characteristics
Minimum breakdown voltage at 100µA
T
A
= 25
O
C unless otherwise noted.
V
(BR)
Vc
I
D
530
760
1.0
650
90
7.5
550
V
V
µA
mV°C
pF
Max. clamping voltage at 400mA, 10/1000µs
-
waveform
Maximum DC reverse leakage current at V
WM
Typical temperature coefficient of V
(BR)
Typical capacitance
(4)
at 0V
at 200V
C
J
Notes:
(1) Non repetitive current pulse per Fig.3 and derated above 25
O
C per Fig. 2
(2) Mounted on 5.0mm
2
copper pads to each terminal
(3) Lead temperature at 75
O
C = T
L
(4) Measured at 1MH
Z
(5) Peak pulse power waveform is 10/1000µs.
Document Number 88391
03-Mar-03
www.vishay.com
1
SMAJ530 and SMAJ550
Vishay Semiconductors
formerly General Semiconductor
Ratings and
Characteristic Curves
(T
100
A
= 25°C unless otherwise noted)
Fig. 1 – Peak Pulse Power Rating Curve
P
PPM
– Peak Pulse Power (kW)
Non-repetitive Pulse
Waveform shown in Fig. 3
T
A
= 25°C
10
Fig. 2 – Pulse Derating Curve
Peak Pulse Power (P
PP
) or Current (I
PP
)
Derating in Percentage, %
100
75
50
1
25
0.1
0.1µs
1.0µs
10µs
100µs
1.0ms
10ms
0
0
25
50
75
100
125
150
175
td – Pulse Width (sec.)
T
A
– Ambient Temperature (°C)
Fig. 3 – Pulse Waveform
150
I
PPM
– Peak Pulse Current, % I
RSM
tr = 10µsec.
Peak Value
I
PPM
100
T
J
= 25°C
Pulse Width (td)
is defined as the point
where the peak current
decays to 50% of I
PPM
Half Value – IPP
2
I
PPM
50
10/1000µsec. Waveform
as defined by R.E.A.
td
0
0
1.0
2.0
3.0
4.0
t – Time (ms)
Application Notes
•
Respect Thermal Resistance (PCB Layout) – as the temperature coefficient also contributes to the clamping voltage.
•
Select minimum breakdown voltage, so you get acceptable power dissipation and PCB tie point temperature.
Devices with higher breakdown voltage will have a shorter conduction time and will dissipate less power.
•
Clamping voltage is influenced by internal resistance – design approximation is 7V per 100mA slope.
•
Keep temperature of TVS lower than TOPSwitch
as a recommendation.
•
Maximum current is determined by the maximum T
J
and can be higher than 300mA.
Contact supplier for different clamping voltage / current arrangements.
•
Minimum breakdown voltage can be customized for other applications. Contact supplier.
•
TOPSwitch
is a registered trademark of Power Integrations, Inc.
www.vishay.com
2
Document Number 88391
03-Mar-03
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
