DATASHEET
TM
TM
Programmable Rambus
General Description
XDR
Clock Generator
Features
•
•
•
•
•
ICS9220B
The
ICS9220
clock generator provides Programmable clock
signals to support the Rambus XDR
TM
memory subsystem
and Redwood logic interface. The
ICS9220
has been
optimized for 100MHz reference input that may or may not be
modulated for spread spectrum. The
ICS9220
provides 2
differential clock pairs in a space saving 28-pin TSSOP
package and provides an off-the-shelf high-performance
interface solution.
Figure 1 shows the major components of the
ICS9220
XDR
Clock Generator. These include the a PLL, a Bypass
Multiplexer and two differential output buffers. The outputs
can be disabled by a logic low on the OE pin. An output is
enabled by the combination of the OE pin being high, and 1 •
in its SMBus Output control register bit.
•
The PLL receives a reference clock, CLK_INT/C and outputs
a clock signal at a frequency equal to the input frequency
times a multiplier. Table 2 shows the multipliers selectable
via the SMBus interface. This clock signal is then fed to the
differential output buffers to drive the enabled clocks. Disabled
outputs are set to Hi-Z. The Bypass mode routes the input
clock, CLK_INT/C, directly to the differential output buffers,
bypassing the PLL.
Up to four
ICS9220
devices can be cascaded on the same
SMBus. Table 3 shows the SMBus addressing and control for
the four devices.
300 - 700 MHz clock source
2 open-drain differential output drives with short
term jitter < 40ps
Spread spectrum compatible
Reference clock is differential or single-ended
100MHz
SMBus programmability for:
- frequency multiplier
- output enable
- operating mode
Support systems where XDR subsystem is
asynchronous to other system clocks
2.5V power supply
Block Diagram
OE
OE
RegA
BYPASS#/PLL
Pin Configuration
AVDD2.5
AGND
IREFY
AGND
CLK_INT
CLK_INC
VDD2.5
GND
SMBCLK
SMBDAT
OE
AS1
AS2
BYPASS#/PLL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD2.5
GND
GND
ODCLK_T0
ODCLK_C0
GND
VDD2.5
VDD2.5
GND
ODCLK_T1
ODCLK_C1
GND
GND
VDD2.5
ODCLK_T0
ODCLK_C0
Bypass
MUX
OE
RegB
ODCLK_T1
ODCLK_C1
CLK_INT
CLK_INC
SMBCLK
PLL
SMBDAT
AS1
AS2
28-Pin 4.4mm TSSOP
IDT
TM
Programmable Rambus
TM
XDR
TM
Clock Generator
1427A
—
01/26/10
1
ICS9220
ICS9220B
Programmable Rambus
TM
XDR
TM
Clock Generator
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
AVDD2.5
AGND
IREFY
AGND
CLK_INT
CLK_INC
VDD2.5
GND
SMBCLK
SMBDAT
OE
AS1
AS2
BYPASS#/PLL
VDD2.5
GND
GND
ODCLK_C1
ODCLK_T1
GND
VDD2.5
VDD2.5
GND
ODCLK_C0
ODCLK_T0
GND
GND
VDD2.5
PIN TYPE
PWR
PWR
IN
PWR
IN
IN
PWR
PWR
IN
I/O
IN
IN
IN
IN
PWR
PWR
PWR
OUT
OUT
PWR
PWR
PWR
PWR
OUT
OUT
PWR
PWR
PWR
DESCRIPTION
2.5V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
This pin establishes the reference current for the differential
clock pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current.
Analog Ground pin for Core PLL
"True" reference clock input.
"Complementary" reference clock input.
Power supply, nominal 2.5V
Ground pin.
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Default SMBus Address Select.
Default SMBus Address Select.
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Power supply, nominal 2.5V
Ground pin.
Ground pin.
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Ground pin.
Power supply, nominal 2.5V
Power supply, nominal 2.5V
Ground pin.
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Ground pin.
Ground pin.
Power supply, nominal 2.5V
IDT
TM
Programmable Rambus
TM
XDR
TM
Clock Generator
1427A
—
01/26/10
2
ICS9220B
Programmable Rambus
TM
XDR
TM
Clock Generator
General SMBus serial interface information for the ICS9220B
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address per table 3
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address per table 3
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address per table 3
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host)
starT bit
T
Slave Address table 3
WR
W Rite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Sla ve/Re ce ive r)
Index Block Read Operation
Controlle r (Host)
T
starT bit
Slave Address table 3
WR
W Rite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address table 3
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
Byte N + X - 1
N
P
Not acknowledge
stoP bit
ACK
ICS (Sla ve/Re ce ive r)
Byte N + X - 1
ACK
P
stoP bit
IDT
TM
Programmable Rambus
TM
XDR
TM
Clock Generator
1427A
—
01/26/10
3
ICS9220B
Programmable Rambus
TM
XDR
TM
Clock Generator
I C Table: Output Enable Control Register
2
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
Pin #
-
-
-
-
-
-
-
-
Name
Test Mode
Reserved
Reserved
Reserved
Reserved
Reserved
ODCLK_T/C1
ODCLK_T/C0
Control Function
Reserved For Vendor
Reserved
Reserved
Reserved
Reserved
Reserved
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
-
-
-
-
-
Disable
Disable
1
Enable
-
-
-
-
-
Enable
Enable
PWD
0
0
0
0
0
0
1
1
I C Table: Frequency Multiplier Control Register
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
Pin #
-
-
-
-
-
-
-
-
Name
Reserved
AS1
AS2
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
Reserved
SMBus Address Select
SMBus Address Select
Reserved
Reserved
Reserved
Reserved
Reserved
Type
R
R
R
R
R
R
R
R
0
-
See Table 2
-
-
-
-
-
1
-
PWD
0
x
x
-
-
-
-
-
0
0
0
0
0
I C Table: Vendor & Revision ID Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
Pin #
-
-
-
-
-
-
-
-
Name
RID 3
RID 2
RID 1
RID 0
VID 3
VID 2
VID 1
VID 0
Control Function
Revision ID
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
1
Vendor ID
I C Table: Frequency Control Register
Byte 3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Pin #
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
0
IDT
TM
Programmable Rambus
TM
XDR
TM
Clock Generator
1427A
—
01/26/10
4
ICS9220B
Programmable Rambus
TM
XDR
TM
Clock Generator
I C Table: Frequency Control Register
2
Byte 4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
Pin #
-
-
-
-
-
-
-
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
0
I C Table: VCO Frequency Control Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Pin #
Name
Reserved
Reserved
Reserved
Reserved
M DIV3
M DIV2
M DIV1
M DIV0
Control Function
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
0
-
-
-
-
1
-
-
-
-
PWD
0
0
0
0
0
0
1
0
M Divider Programming
b(3:0)
RW
RW
RW
The decimal representation of
M and N Divider in Byte 5 and
6 will configure the PLL VCO
frequency. VCO frequency =
100 x
{[NDIV(5:0)+2]/[MDIV(3:0)+2]}
I C Table: VCO Frequency Control Register
2
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Pin #
Name
Reserved
Reserved
N DIV5
N DIV4
N DIV3
N DIV2
N DIV1
N DIV0
Control Function
Type
RW
RW
RW
0
-
-
1
-
-
PWD
0
0
0
0
1
0
1
0
N Divider Programming
b(5:0)
RW
RW
RW
RW
RW
The decimal representation of
M and N Divider in Byte 5 and
6 will configure the PLL VCO
frequency. VCO frequency =
100 x
{[NDIV(5:0)+2]/[MDIV(3:0)+2]}
IDT
TM
Programmable Rambus
TM
XDR
TM
Clock Generator
1427A
—
01/26/10
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
