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MTP10N10EL
Preferred Device
Power MOSFET
10 A, 100 V, Logic Level, N−Channel TO−220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Features
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10 A, 100 V
R
DS(on)
= 0.22
W
N−Channel
D
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
•
Pb−Free Package is Available
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MW)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (t
p
≤
10 ms)
Drain Current
− Continuous @ T
C
= 25°C
− Continuous @ T
C
= 100°C
− Single Pulse (t
p
≤
10
ms)
Total Power Dissipation @ T
C
= 25°C
Derate above 25°C
Total Power Dissipation @ T
C
= 25°C
(Note 1)
Operating and Storage Temperature
Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 5.0 Vdc, Peak
I
L
= 10 Adc, L = 1.0 mH, R
G
= 25
W)
Thermal Resistance
− Junction−to−Case°
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 secs
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
Value
100
100
±
15
±
20
10
6.0
35
40
0.32
1.75
−55 to
150
50
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
4
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
1
2
3
TO−220AB
CASE 221A
STYLE 5
MTP10N10EL
LLYWW
1
Gate
2
Drain
3
Source
T
J
, T
stg
E
AS
MTP10N10EL
LL
Y
WW
= Device Code
= Location Code
= Year
= Work Week
°C/W
R
qJC
R
qJA
R
qJA
T
L
3.13
100
71.4
260
°C
ORDERING INFORMATION
Device
MTP10N10EL
MTP10N10ELG
Package
TO−220AB
TO−220AB
(Pb−Free)
Shipping
50 Units/Rail
50 Units/Rail
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2005
1
March, 2005 − Rev. 4
Publication Order Number:
MTP10N10EL/D
MTP10N10EL
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 100 Vdc, V
GS
= 0 Vdc)
°
(V
DS
= 100 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±15
Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Threshold Temperature Coefficient (Negative)m
Static Drain−to−Source On−Resistance (V
GS
= 5.0 Vdc, I
D
= 5.0 Adc)
Drain−to−Source On−Voltage
(V
GS
= 5.0 Vdc, I
D
= 10 Adc)
°
(V
GS
= 5.0 Vdc, I
D
= 5.0 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 8.0 Vdc, I
D
= 5.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DS
= 80 Vdc, I
D
= 10 Adc,
V
GS
= 5.0 Vdc)
)
(V
DD
= 50 Vdc, I
D
= 10 Adc,
V
GS
= 5.0 Vdc, R
g
= 9.1
W)
)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 2)
(I
S
= 10 Adc, V
GS
= 0 Vdc)
(I
S
= 10 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
−
−
t
rr
(I
S
= 10 Adc, V
GS
= 0 Vdc,
Adc
Vdc
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored
Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad.)
2. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2.0%.
3. Switching characteristics are independent of operating junction temperature.
L
d
−
L
s
−
7.5
−
4.5
−
nH
t
a
t
b
Q
RR
−
−
−
−
0.98
0.898
124.7
86
38.7
0.539
1.6
−
−
−
−
−
mC
ns
s
Vdc
−
−
−
−
−
−
−
−
11
74
17
38
9.3
2.56
4.4
4.6
−
−
20
150
30
80
15
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
Vd
Vd
f = 1 0 MHz)
1.0
C
iss
C
oss
C
rss
−
−
−
741
175
18.9
1040
250
40
pF
V
GS(th)
1.0
−
R
DS(on)
V
DS(on)
−
−
g
FS
Symbol
Min
Typ
Max
Unit
V
(BR)DSS
100
−
I
DSS
−
−
I
GSS
−
−
−
−
10
100
100
−
115
−
−
Vdc
mV/°C
mAdc
nAdc
Vdc
1.45
4.0
0.17
1.85
−
7.9
2.0
−
0.22
2.6
2.3
−
mhos
mV/°C
Ohm
Vdc
−
5.0
Reverse Recovery Time
e e se eco e y
e
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2
MTP10N10EL
TYPICAL ELECTRICAL CHARACTERISTICS
20
ID , DRAIN CURRENT (AMPS)
20
5V
ID , DRAIN CURRENT (AMPS)
4.5 V
4V
10
3.5 V
5
3V
2V
0
0
1
2
3
4
5
0
1
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
2
3
4
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
5
15
25°C
10
T
J
= 100°C
T
J
= 25°C
V
GS
= 10 V
7V
V
DS
≥
5 V
−55°C
15
5
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.35
V
GS
= 5 V
0.25
T
J
= 25°C
100°C
0.25
T
J
= 25°C
0.15
−55°C
0.2
V
GS
= 5 V
10 V
0.15
0.05
0
5
10
I
D
, DRAIN CURRENT (AMPS)
15
20
0.1
0
5
10
I
D
, DRAIN CURRENT (AMPS)
15
20
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2
V
GS
= 5 V
I
D
= 5 A
1.5
I DSS , LEAKAGE (nA)
100
V
GS
= 0 V
T
J
= 125°C
1
10
100°C
0.5
0
− 50
− 25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
1
0
80
20
40
60
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
Figure 5. On−Resistance Variation
with Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTP10N10EL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
1800
1600
1400
C, CAPACITANCE (pF)
1200
1000
800
600
400
200
0
10
5
V
GS
0
V
DS
5
10
C
oss
C
rss
15
20
25
C
rss
C
iss
C
iss
V
DS
= 0 V
V
GS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
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