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SN54LV161A, SN74LV161A
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404 – APRIL 1998
D
EPIC
(Enhanced-Performance Implanted
D
D
D
D
D
D
D
CMOS) Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
, T
A
= 25°C
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
SN54LV161A . . . J OR W PACKAGE
SN74LV161A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
CLR
CLK
A
B
C
D
ENP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
SN54LV161A . . . FK PACKAGE
(TOP VIEW)
The ’LV161A devices are 4-bit synchronous
binary counters designed for 2-V to 5.5-V V
CC
operation.
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. Synchronous
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when so
instructed by the count-enable (ENP, ENT) inputs
and internal gating. This mode of operation
eliminates the output counting spikes that
normally are associated with synchronous
(ripple-clock) counters. A buffered clock (CLK)
input triggers the four flip-flops on the rising
(positive-going) edge of the clock waveform.
5
6
7
8
17
16
15
14
9 10 11 12 13
NC – No internal connection
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV161A devices is asynchronous. A low level at the clear (CLR) input sets all four
of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q
A
high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright
1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
7–111
PRODUCT PREVIEW
description
A
B
NC
C
D
CLK
CLR
NC
V
CC
RCO
4
3 2 1 20 19
18
Q
A
Q
B
NC
Q
C
Q
D
LOAD
ENT
ENP
GND
NC
SN54LV161A, SN74LV161A
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404 – APRIL 1998
description (continued)
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54LV161A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV161A is characterized for operation from –40°C to 85°C.
logic symbol
†
1
9
10
7
2
3
4
5
6
CTRDIV16
CT=0
M1
M2
G3
G4
C5/2,3,4+
1,5D
[1]
[2]
[4]
[8]
14
13
12
11
QA
QB
QC
QD
15
CLR
LOAD
ENT
ENP
CLK
3CT=15
RCO
PRODUCT PREVIEW
A
B
C
D
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
7–112
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54LV161A, SN74LV161A
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404 – APRIL 1998
logic diagram (positive logic)
LOAD
ENT
ENP
9
10
7
LD†
CK†
CLK
CLR
2
1
CK
R
LD
15
RCO
A
3
B
4
M1
G2
1, 2T/1C3
G4
3D
4R
13
QB
C
5
M1
G2
1, 2T/1C3
G4
3D
4R
12
QC
D
6
M1
G2
1, 2T/1C3
G4
3D
4R
11
QD
† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
7–113
PRODUCT PREVIEW
M1
G2
1, 2T/1C3
G4
3D
4R
14
QA
SN54LV161A, SN74LV161A
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404 – APRIL 1998
logic symbol, each D/T flip-flop
LD (Load)
TE (Toggle Enable)
CK (Clock)
M1
G2
1, 2T/1C3
G4
3D
4R
Q (Output)
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
LD†
PRODUCT PREVIEW
TG
TG
LD†
D
TG
TG
TG
CK†
CK†
TG
Q
CK†
R
† The origins of LD and CK are shown in the logic diagram of the overall device.
CK†
7–114
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
FPGA/CPLD
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