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SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256
×
9, 512
×
9, 1024
×
9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
D
D
D
D
D
D
D
D
D
D
Reads and Writes Can Be Asynchronous
or Coincident
Organization:
– SN74ACT7200L – 256
×
9
– SN74ACT7201LA – 512
×
9
– SN74ACT7202LA – 1024
×
9
Fast Data Access Times of 15 ns
Read and Write Frequencies up to 40 MHz
Bit-Width and Word-Depth Expansion
Fully Compatible With the
IDT7200/ 7201 / 7202
Retransmit Capability
Empty, Full, and Half-Full Flags
TTL-Compatible Inputs
Available in 28-Pin Plastic DIP (NP),
Small-Outline (DV), and 32-Pin Plastic
J-Leaded Chip-Carrier (RJ) Packages
DV OR NP PACKAGE
(TOP VIEW)
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D4
D5
D6
D7
FL /RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
RJ PACKAGE
(TOP VIEW)
The SN74ACT7200L, SN74ACT7201LA, and
SN74ACT7202LA are constructed with dual-port
SRAM and have internal write and read address
counters to provide data throughput on a first-in,
first-out (FIFO) basis. Write and read operations
are independent and can be asynchronous or
coincident. Empty and full status flags prevent
underflow and overflow of memory, and
depth-expansion logic allows combining the
storage cells of two or more devices into one
FIFO. Word-width expansion is also possible.
Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R)
input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of
15 ns.
D3
D8
W
NC
V
CC
D4
D5
4
description
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
5
6
7
8
9
10
11
12
3 2 1 32 31 30
29
28
27
26
25
24
23
22
13
21
14 15 16 17 18 19 20
D6
D7
NC
FL /RT
RS
EF
XO/HF
Q7
Q6
Q3
Q8
NC – No internal connection
These devices are particularly suited for providing a data channel between two buses operating at
asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in data-
acquisition systems, temporary storage elements between buses and magnetic or optical memories, and
queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus
a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for
retransmitting previously read data when a device is not used in depth expansion.
The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are characterized for operation from 0°C
to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
GND
NC
R
Q4
Q5
1
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256
×
9, 512
×
9, 1024
×
9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
SN74ACT7200L logic symbol
†
FIFO 256
×
9
Φ
SN74ACT7200L
22
RS
W
1
2,4 CT = 0 (RST)
6 (WR PNTR)
6 C1
G2
XI
FL /RT
7
23
(EXPAND)
(1ST LOAD)
2,4 (REXMIT)
15
R
5 (RD PNTR)
5EN3
G4
(CT = WR PNTR – RD PNTR)
D0
D1
D2
D3
D4
D5
D6
D7
D8
6
5
4
3
27
26
25
24
2
1D
3
9
10
11
12
16
17
18
19
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
(EXPAND)
CT > 128
20
XO/HF
2(CT = 255) G6
4(CT = 255) G6
(CT = 256) G6
(CT = 0) G5
8
FF
21
EF
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256
×
9, 512
×
9, 1024
×
9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
SN74ACT7201LA logic symbol
†
FIFO 512
×
9
Φ
SN74ACT7201LA
22
RS
W
1
2,4 CT = 0 (RST)
6 (WR PNTR)
6 C1
G2
XI
FL /RT
7
23
(EXPAND)
(1ST LOAD)
2,4 (REXMIT)
15
R
5 (RD PNTR)
5EN3
G4
(CT = WR PNTR – RD PNTR)
D0
D1
D2
D3
D4
D5
D6
D7
D8
6
5
4
3
27
26
25
24
2
1D
3
9
10
11
12
16
17
18
19
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
(EXPAND)
CT > 256
20
XO/HF
2(CT = 511) G6
4(CT = 511) G6
(CT = 512) G6
(CT = 0) G5
8
FF
21
EF
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256
×
9, 512
×
9, 1024
×
9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
SN74ACT7202LA logic symbol
†
FIFO 1024
×
9
Φ
SN74ACT7202LA
22
RS
W
1
2,4 CT = 0 (RST)
6 (WR PNTR)
6 C1
G2
XI
FL /RT
7
23
(EXPAND)
(1ST LOAD)
2,4 (REXMIT)
15
R
5 (RD PNTR)
5EN3
G4
(CT = WR PNTR – RD PNTR)
D0
D1
D2
D3
D4
D5
D6
D7
D8
6
5
4
3
27
26
25
24
2
1D
3
9
10
11
12
16
17
18
19
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
(EXPAND)
CT > 512
20
XO/HF
2(CT = 1023) G6
4(CT = 1023) G6
(CT = 1024) G6
(CT = 0) G5
8
FF
21
EF
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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