Technical Data
MPC8250EC/D
Rev. 0.9 8/2003
MPC8250
Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC8250 PowerQUICC II™
communications processor.
The following topics are addressed:
Topic
Section 1.1, “Features”
Section 1.2, “Electrical and Thermal Characteristics”
Section 1.2.1, “DC Electrical Characteristics”
Section 1.2.2, “Thermal Characteristics”
Section 1.2.3, “Power Considerations”
Section 1.2.4, “AC Electrical Characteristics”
Section 1.3, “Clock Configuration Modes”
Section 1.3.1, “Local Bus Mode”
Section 1.3.2, “PCI Mode”
Section 1.4, “Pinout”
Section 1.5, “Package Description”
Section 1.6, “Ordering Information”
Page
2
5
5
10
10
11
19
19
22
28
53
56
The MPC8250 is available in two packages—the standard ZU package (480 TBGA) and an
alternate VR package (516 PBGA)—as described in Section 1.4, “Pinout,” and Section 1.5,
“Package Description.” For more information on VR packages, contact your Motorola sales
office. Note that throughout this document references to the MPC8250 are inclusive of its VR
version unless otherwise specified.
NOTE: Document Revision History
Changes to this document are summarized in Table 23 on
page 56.
Features
Figure 1 shows the block diagram for the MPC8250.
16 Kbytes
I-Cache
I-MMU
G2 Core
System Interface Unit
(SIU)
16 Kbytes
D-Cache
D-MMU
Bus Interface Unit
60x-to-PCI
Bridge
60x-to-Local
Bridge
Memory Controller
Timers
Parallel I/O
Baud Rate
Generators
32-bit RISC Microcontroller
and Program ROM
4 Virtual
IDMAs
System Functions
Interrupt
Controller
32 Kbytes
Dual-Port RAM
Serial
DMAs
Clock Counter
60x Bus
PCI Bus
32 bits, up to 66 MHz
or
Local Bus
32 bits, up to 66 MHz
Communication Processor Module (CPM)
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
Time Slot Assigner
Serial Interface
4 TDM Ports
3 MII
Ports
Non-Multiplexed
I/O
Figure 1. MPC8250 Block Diagram
1.1
•
•
Features
Footprint-compatible with the MPC8260
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–200 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
The major features of the MPC8250 are as follows:
2
MPC8250 Hardware Specifications
MOTOROLA
Features
•
•
•
•
•
Separate power supply for internal logic (1.8 V) and for I/O (3.3V)
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
•
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
•
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
•
CPU core can be disabled and the device can be used in slave mode to an external core
MOTOROLA
MPC8250 Hardware Specifications
3
Features
•
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible
support for communications protocols
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– Transparent
– HDLC—Up to T3 rates (clear channel)
— One multichannel controller (MCC2)
– Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four
subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I
2
C) controller (identical to the MPC860 I
2
C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to four TDM interfaces
– Supports one group of four TDM channels
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
4
MPC8250 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
•
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
PCI bridge
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Periphera
l
capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8265A) required by the PCI standard as well as message and
doorbell registers
— Supports the I
2
O standard
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specification
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
1.2
1.2.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8250.
This section describes the DC electrical characteristics for the MPC8250. Table 1 shows the maximum
electrical ratings.
MOTOROLA
MPC8250 Hardware Specifications
5
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