GS832218/36/72(B/E/C)-xxxV
119-, 165-, & 209-Pin BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-, 165-, and 209-bump BGA package
• RoHS-compliant packages available
2M x 18, 1M x 36, 512K x 72
36Mb S/DCD Sync Burst SRAMs
250 MHz–133 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Applications
The GS832218/36/72-xxxV is a
37,748,736
-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Functional Description
Re
co
m
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Ne
w
me
nd
ed
for
Parameter Synopsis
-250
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
3.0
4.0
285
350
440
6.5
6.5
205
235
315
De
sig
-225 -200 -166 -150 -133 Unit
3.0
4.4
265
320
410
7.0
7.0
195
225
295
3.0
5.0
245
295
370
7.5
7.5
185
210
265
3.5
6.0
220
260
320
8.0
8.0
175
200
255
3.8
6.7
210
240
300
8.5
8.5
165
190
240
4.0
7.5
185
215
265
8.5
8.5
155
175
230
ns
ns
mA
mA
mA
ns
ns
mA
mA
mA
No
t
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.07 9/2008
1/42
n—
Di
sco
nt
inu
ed
Pr
od
u
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS832218/36/72-xxxV is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Core and Interface Voltages
The GS832218/36/72-xxxV operates on a 1.8 V or 2.5 V power
supply. All inputs are 1.8 V or 2.5 V compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 1.8 V or 2.5 V compatible.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2003, GSI Technology
GS832218/36/72(B/E/C)-xxxV
GS832272C-xxxV 209-Bump BGA Pin Description
Symbol
A
0
, A
1
An
DQ
A
DQ
B
DQ
C
DQ
D
DQ
E
DQ
F
DQ
G
DQ
H
B
A
, B
B
B
C
,B
D
B
E
, B
F
, B
G
,B
H
NC
CK
GW
E
1
E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
SCD
MCH
MCL
BW
ZQ
TMS
TDI
TDO
TCK
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
I/O
I
I
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
I/Os; active low
No Connect
Byte Write Enable for DQ
E
, DQ
F
, DQ
G
, DQ
H
I/Os; active low
Clock Input Signal; active high
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Global Write Enable—Writes all bytes; active low
me
nd
ed
for
Ne
w
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
Must Connect Low
Byte Enable; active low
Re
co
m
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
No
t
I
I
O
I
Rev: 1.07 9/2008
3/42
De
sig
Burst address counter advance enable; active low
n—
Di
sco
nt
inu
ed
Pr
od
u
Data Input and Output pins
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2003, GSI Technology
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
