KS57C0502/C0504/P0504 MICROCONTROLLER
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
The KS57C0502/C0504 single-chip CMOS microcontroller has been designed for high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The KS57P0504 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are
the same to KS57C0502/C0504. With a four-channel comparator, eight LED direct drive pins, serial I/O
interface, and its versatile 8-bit timer/counter, the KS57C0502/C0504 offers an excellent design solution for a
wide variety of general-purpose applications.
Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast re-
sponse to internal and external events. In addition, the KS57C0502/C0504's advanced CMOS technology
provides for very low power consumption and a wide operating voltage range — all at a very low cost.
FEATURES SUMMARY
MEMORY
512
×
4-bit data memory (RAM)
2048
×
8-bit program memory (ROM):KS57C0502
4096
×
8-bit program memory (ROM):KS57C0504
24 I/O PINS
I/O: 18 pins, including 8 high current pins
Input only: 6 pins
COMPARATOR
4-channel mode:
Internal reference (4-bit resolution)
16-step variable reference voltage
3-channel mode:
External reference
150 mV resolution (worst case)
8-BIT BASIC TIMER
Programmable interval timer
Watch-dog timer
8-BIT TIMER/COUNTER
Programmable interval timer
External event counter function
Timer/counter clock output to TCLO0 pin
WATCH TIMER
Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz
4 frequency outputs to BUZ pin
8-BIT SERIAL I/O INTERFACE
8-bit transmit/receive mode
8-bit receive-only mode
LSB-first or MSB-first transmission selectable
Internal or external clock source
BIT SEQUENTIAL CARRIER
Supports 16-bit serial data transfer in arbitrary
format
INTERRUPTS
Two external interrupt vectors
Three internal interrupt vectors
Two quasi-interrupts
MEMORY-MAPPED I/O STRUCTURE
Data memory bank 15
TWO POWER-DOWN MODES
Idle mode: Only CPU clock stops
Stop mode: System clock stops
OSCILLATION SOURCES
Crystal, Ceramic for system clock
Crystal/ceramic: 0.4 - 6.0 MHz
CPU clock divider circuit (by 4. 8, or 64)
INSTRUCTION EXECUTION TIMES
0.95, 1.91, 15.3 µs at 4.19 MHz
0.67, 1.33, 10.7 µs at 6.0 MHz
OPERATING TEMPERATURE
– 40
°
C to 85
°
C
OPERATING VOLTAGE RANGE
1.8 V to 5.5 V
PACKAGE TYPE
30 SDIP, 32 SOP
1–1
PRODUCT OVERVIEW
KS57C0502/C0504/P0504 MICROCONTROLLER
FUNCTION OVERVIEW
SAM47 CPU
All KS57-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address
up to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical,
and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two
cycles.
CPU REGISTERS
Program Counter
A 11-bit program counter (PC) stores addresses for instruction fetch during program execution. Usually, the
PC is incremented by the number of bytes of the instruction being fetched. An exception is the 1-byte instruction
REF which is used to reference instructions stored in a look-up table in the ROM. Whenever a reset operation or
an interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC13–12 is reserved to support
future expansion of the device's ROM size.
Stack Pointer
An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in the general-
purpose data memory bank 0. The SP is read or written by 8-bit instructions and SP bit 0 must always be set to
logic zero.
During an interrupt or a subroutine call, the PC value and the PSW are saved to the stack area in RAM. When
the service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruc-
tion is executed.
The stack pointer can access the stack regardless of data memory access enable flag status. Since the reset
value of the stack pointer is not defined in firmware, it is recommended that the stack pointer be initialized to 00H
by program code. This sets the first register of the stack area to data memory location 0FFH.
PROGRAM MEMORY
In its standard configuration, the 4096
×
8-bit ROM is divided into three functional areas:
— 16-byte area for vector addresses
— 96-byte instruction reference area
— 1920-byte general purpose area (KS57C0502)
— 3968-byte general purpose area (KS57C0504)
The vector address area is used mostly during reset operations and interrupts. These 16 bytes can also be
used as general-purpose ROM.
The REF instruction references 2
×
1-byte and 2-byte instructions stored in locations 0020H–007FH. The REF
instruction can also reference three-byte instructions such as JP or CALL. In order for REF to be able to reference
these instructions, however, JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is is
written to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused
locations in the instruction reference area can be allocated to general-purpose use.
1–2
KS57C0502/C0504/P0504 MICROCONTROLLER
PRODUCT OVERVIEW
DATA MEMORY
Overview
Data memory is organized into three areas:
— 32
×
4-bit working registers
— 224
×
4-bit general-purpose area in bank 0
— 256
×
4-bit general-purpose area in bank 1
— 128
×
4-bit area in bank 15 for memory-mapped I/O addresses
Data stored in data memory can be manipulated by 1-, 4-, and 8-bit instructions.
Data memory is organized into two memory banks — bank 0, bank 1 and bank 15. The select memory bank
instruction (SMB) selects the bank to be used as working data memory. After power-on reset operation,
initialization values for data memory must be redefined by code.
Data Memory Addressing Modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1 or 15.
When the EMB flag is logic zero, restricted area can be accessed. When the EMB flag is set to logic one, all
two data memory banks can be accessed according to the current SMB value. The EMB = "0" addressing mode
is used for normal program execution, whereas the EMB = "1" mode is commonly used for interrupts,
subroutines, mapped I/O, and repetitive access of specific RAM addresses.
Working Registers
The RAM's working register area in data memory bank 0 is further divided into four
register
banks. Each
register bank has eight 4-bit registers that are addressable either by 1-bit or 4-bit instructions. Paired 4-bit
registers can be addressed as double registers by 8-bit instructions.
Register A is the 4-bit accumulator and double register EA is the 8-bit extended accumulator. Double registers
WX, WL, and HL are used as data pointers for indirect addressing. Unused working registers can be used as
general-purpose memory.
To limit the possibility of data corruption due to incorrect register bank addressing, register bank 0 is usually
used by the main program and banks 1, 2, and 3 for interrupt service routines.
1–3
PRODUCT OVERVIEW
KS57C0502/C0504/P0504 MICROCONTROLLER
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory enable flags.
Before an interrupt or subroutine is processed, the PSW is pushed onto the stack in data memory bank 0.
When the service routine is completed, the PSW values are restored.
IS1
C
IS0
SC2
EMB
SC1
ERB
SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. You can address the skip condition flags
(SC0–SC2) using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit registers store address values used to access specific memory and register banks: the select
memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instruction selects a data memory bank (0 or 15) and stores the upper four bits of the 12-bit data
memory address in the SMB register. To select register bank 0, 1, 2, or 3, and store the address data in the SRB,
you use the instruction 'SRB n'.
The instructions "PUSH SB" and "POP SB" move SRB and SMB values to and from the stack for interrupts
and subroutines.
CLOCK CIRCUITS
System oscillation circuit generates the internal clock signals for the CPU and peripheral hardware.
The system clock can use a crystal, or ceramic oscillation source, or an externally-generated clock signal. To
drive KS57C0502/C0504 using an external clock source, the external clock signal should be input to X
in
, and its
inverted signal to X
out
.
4-bit power control register controls the oscillation on/off, and select the CPU clock. The internal system clock
signal (fx) can be divided internally to produce three CPU clock frequencies — fx/4, fx/8, or fx/64.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, and INTS) or externally by
peripheral devices (INT0 and INT1). There are two quasi-interrupts: INTK and INTW. INTK (KS0–KS2) detects
falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91 milliseconds. The
following components support interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
1–4
KS57C0502/C0504/P0504 MICROCONTROLLER
PRODUCT OVERVIEW
POWER-DOWN
To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates
idle mode; the STOP instruction initiates stop mode.
In idle mode, the CPU clock stops while peripherals continue to operate normally. In stop mode, system clock
oscillation stops completely, halting all operations except for a few basic peripheral functions. A power-down is
or by an interrupt (with exception of the external interrupt INT0).
terminated either by a
RESET
When
is input during normal operation or during power-down mode, a reset operation is initiated and the
CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has
elapsed, normal CPU operation resumes.
I/O PORTS
The KS57C0502/C0504 has seven I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–
FF6H in bank 15 of the RAM. There are 6 input pins and 18 configurable I/O pins including 8 high current I/O pins
for a total of 24 I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding
address using bit manipulation instructions.
TIMERS and TIMER/COUNTER
The timer function has three main components: an 8-bit basic timer, an 8-bit timer/counter, and a watch timer.
The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected internal clock
frequency.
The programmable 8-bit timer/counter is used for counting events, modifying internal clock frequencies, and
dividing external clock signals. The 8-bit timer/counter generates a clock signal ( ) for the serial I/O interface.
The watch timer consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider
circuit. Its functions include real-time, watch-time measurement, and clock generation for frequency output for
buzzer sound.
SERIAL I/O INTERFACE
The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The
serial interface has the following functional components:
— 8-bit mode register
— Clock selector circuit
— 8-bit buffer register
— 3-bit serial clock counter
The serial I/O circuit can be set to transmit-and-receive, or to receive-only mode. MSB-first or LSB-first
transmission is also selectable.
The serial interface can operate with an internal or an external clock source, or using the clock signal
generated by the 8-bit timer/counter. Transmission frequency can be modified by setting the appropriate bits in
the SIO mode register.
1–5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
