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IDT74LVCHR16501APV8

产品描述Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56
产品类别逻辑    逻辑   
文件大小157KB,共7页
制造商IDT (Integrated Device Technology)
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IDT74LVCHR16501APV8概述

Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56

IDT74LVCHR16501APV8规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码SSOP
包装说明SSOP,
针数56
Reach Compliance Codecompliant
其他特性WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列LVC/LCX/Z
JESD-30 代码R-PDSO-G56
长度18.415 mm
逻辑集成电路类型REGISTERED BUS TRANSCEIVER
位数18
功能数量1
端口数量2
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE WITH SERIES RESISTOR
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码SSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度)NOT SPECIFIED
传播延迟(tpd)8 ns
认证状态Not Qualified
座面最大高度2.794 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.7 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式GULL WING
端子节距0.635 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度7.493 mm

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IDT74LVCHR16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER W/ 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
IDT74LVCHR16501A
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
FEATURES:
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
Extended commercial range of -40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4µ W typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
DESCRIPTION:
The LVCHR16501A 18-bit registered transceiver is built using advanced
dual metal CMOS technology. This high-speed, low power 18-bit registered
bus transceiver combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes. Data flow in each direction
is controlled by output-enable (OEAB and
OEBA),
latch enable (LEAB and
LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in transparent mode when LEAB is high. When LEAB is low,
the A data is latched if CLKAB is held at a high or low logic level. If LEAB
is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition
of CLKAB. OEAB performs the output enable function on the B port. Data
flow from B port to A port is similar but requires using
OEBA,
LEBA and
CLKBA. Flow-through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The LVCHR16501A has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been developed to drive
±
12mA at the designated thresholds.
The LVCHR16501A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
Drive Features for LVCHR16501A:
– Balanced Output Drivers: ±12mA
– Low switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
OEA B
CLK BA
1
30
LEB A
OEB A
CLK AB
LEA B
28
27
55
2
C
A
1
3
C
D
54
D
B
1
C
D
C
D
TO 17 OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4893/-
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