FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11316-3E
MEMORY
CMOS
4 M
×
4 BIT
FAST PAGE MODE DYNAMIC RAM
MB8117400B-50/-60
CMOS 4,194,304
×
4 Bit Fast Mode Dynamic RAM
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DESCRIPTION
The Fujitsu MB8117400B is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 4-bit increments. The MB8117400B features a “fast page” mode of operation whereby high-
speed random access of up to 2,048
×
4 bits of data within the same row can be selected. The MB8117400B
DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB8117400B is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB8117400B is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for
the MB8117400B are not critical and all inputs are TTL compatible.
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PRODUCT LINE & FEATURES
Parameter
RAS Access Time
Randam Cycle Time
Address Access Time
CAS Access Time
Fast Page Mode Cycle Time
Low Power
Dissipation
Operating Current
Standby Current
MB8117400B-50
50 ns max.
90 ns min.
25 ns min.
13 ns max.
35 ns min.
660 mW max.
MB8117400B-60
60 ns max.
110 ns min.
30 ns max.
15 ns max.
40 ns min.
550 mW max.
11 mW max. (TTL level) / 5.5 mW max. (CMOS level)
• RAS only, CAS-before-RAS, or Hidden
Refresh
• Fast page Mode, Read-Modify-Write
capability
• On chip substrate bias generator for high
performance
• 4,194,304 words
×
4 bits organization
• Silicon gate, CMOS, Advanced Stacked
Capacitor Cell
• All input and output are TTL compatible
• 2048 refresh cycles every 32.8 ms
• Early Write or OE controlled write capability
MB8117400B-50/-60
s
PACKAGE
Plastic SOJ Package
Plastic TSOP (ll) Package
(LCC-26P-M09)
(FPT-26P-M05)
(Normal Bend)
Package and Ordering Information
– 26-pin plastic (300 mil) SOJ, order as MB8117400B-××PJ
– 26-pin plastic (300 mil) TSOP (II) with normal bend leads, order as MB8117400B-××PFTN
2
MB8117400B-50/-60
s
PIN ASSIGNMENTS AND DESCRIPTIONS
26-Pin SOJ
(TOP VIEW)
<LCC-26P-M09>
V
CC
DQ
1
DQ
2
WE
RAS
N.C.
1
2
3
4
5
6
26
25
24
23
22
21
V
SS
DQ
4
DQ
3
CAS
OE
A
9
V
CC
DQ
1
DQ
2
WE
RAS
N.C.
A
10
A
0
A
1
A
2
A
3
V
CC
26-Pin TSOP (ll)
(TOP VIEW)
<Normal Bend: FPT-26P-M05>
26
25
24
23
22
21
V
SS
DQ
4
DQ
3
CAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
1
2
3
4
5
6
1 pin index
A
10
A
0
A
1
A
2
A
3
V
CC
8
9
10
11
12
13
19
18
17
16
15
14
A
8
A
7
A
6
A
5
A
4
V
SS
8
9
10
11
12
13 (Marking side)
19
18
17
16
15
14
Designator
DQ
1
to DQ
4
WE
RAS
A
0
to A
10
V
CC
OE
CAS
V
SS
N.C.
Function
Data Input/ Output
Write enable
Row address strobe
Address inputs
+5 volt power supply
Output enable
Column address strobe
Circuit ground
No Connection
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MB8117400B-50/-60
Fig. 1 – MB8117400B DYNAMIC RAM - BLOCK DIAGRAM
RAS
CAS
Clock
Gen #1
Write
Clock
Gen
Mode
Control
WE
Clock
Gen #2
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
OE
A
9
A
10
Refresh
Address
Counter
Substrate
Bias Gen
Address
Buffer
&
Pre-
Decoder
Row
Decoder
•
•
•
Column
Decoder
Sense Ampl &
I/O Gate
•
•
•
Data Out
Buffer
Data In
Buffer
DQ
1
to
DQ
4
16,777,216 Bit
Storage
Cell
V
CC
V
SS
4
MB8117400B-50/-60
s
FUNCTIONAL TRUTH TABLE
Operation Mode
Standby
Read Cycle
Write Cycle
(Early Write)
Read-Modify-
Write Cycle
RAS-only
Refresh Cycle
CAS-before-
RAS Refresh
Cycle
Hidden Refresh
Cycle
Clock Input
RAS
H
L
L
L
L
L
H→L
CAS
H
L
L
L
H
L
L
WE
X
H
L
OE
X
L
X
Address Input
Row
—
Valid
Valid
Valid
Valid
—
—
Column
—
Valid
Valid
Valid
—
—
—
Input Data
Input
—
—
Valid
Valid
—
—
—
Output
High-Z
Valid
High-Z
Valid
High-Z
High-Z
Valid
Refresh
—
Yes *
Yes *
Yes *
Yes
Yes
Yes
t
CSR
≥
t
CSR
(min)
Previous data
is kept.
t
RCS
≥
t
RCS
(min)
t
WCS
≥
t
WCS
(min)
Note
H→L L→H
X
H
H→X
X
X
L
X : “H” or “L”
* : It is impossible in Fast Page Mode.
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FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty-two input bits are required to decode any four of 16,777,216 cell addresses in the memory matrix. Since
only eleven address bits (A
0
to A
10
) are available, the row and column inputs are separately strobed by RAS and
CAS as shown in Figure 1. First, eleven row address bits are input on pins A
0
-through-A
10
and latched with the row
address strobe (RAS) then, eleven column address bits are input and latched with the column address strobe (CAS).
Both row and column addresses must be stable on or before the falling edges of RAS and CAS, respectively. The
address latches are of the flow-through type; thus, address information appearing after t
RAH
(min)+ t
T
is automatically
treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUTS
Input data is written into memory in either of three basic ways–an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ
1
to DQ
4
) is strobed by CAS and the setup/hold times are referenced
to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after
CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.
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