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SN74LS85
4−Bit Magnitude
Comparator
The SN74LS85 is a 4-Bit Magnitude Camparator which compares
two 4-bit words (A, B), each word having four Parallel Inputs
(A
0
−A
3
, B
0
−B
3
); A
3
, B
3
being the most significant inputs. Operation
is not restricted to binary codes, the device will work with any
monotonic code. Three Outputs are provided: “A greater than B”
(O
A > B
), “A less than B” (O
A < B
), “A equal to B” (O
A = B
). Three
Expander Inputs, I
A > B
, I
A < B
, I
A = B
, allow cascading without external
gates. For proper compare operation, the Expander Inputs to the least
significant position must be connected as follows: I
A < B
= I
A > B
= L,
I
A = B
= H. For serial (ripple) expansion, the O
A > B
, O
A < B
and O
A = B
Outputs are connected respectively to the I
A > B
, I
A < B
, and I
A = B
Inputs of the next most significant comparator, as shown in Figure 1.
Refer to Applications section of data sheet for high speed method of
comparing large words.
The Truth Table on the following page describes the operation of the
SN74LS85 under all possible logic conditions. The upper 11 lines
describe the normal operation under all conditions that will occur in a
single device or in a series expansion scheme. The lower five lines
describe the operation under abnormal conditions on the cascading
inputs. These conditions occur when the parallel expansion technique
is used.
•
Easily Expandable
•
Binary or BCD Comparison
•
O
A > B
, O
A < B
, and O
A = B
Outputs Available
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current
−
High
Output Current
−
Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
−0.4
8.0
Unit
V
°C
mA
mA
16
1
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LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
SOEIAJ
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
SN74LS85N
SN74LS85D
SN74LS85DR2
SN74LS85M
SN74LS85MEL
Package
16 Pin DIP
SOIC−16
SOIC−16
SOEIAJ−16
SOEIAJ−16
Shipping
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
See Note 1
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2006
July, 2006
−
Rev. 8
1
Publication Order Number:
SN74LS85/D
SN74LS85
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
A
3
15
B
2
14
A
2
13
A
1
12
B
1
11
A
0
10
B
0
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
B
3
2
I
A<B
3
I
A=B
4
I
A>B
5
6
7
8
O
A>B
O
A=B
O
A<B
GND
LOADING
(Note a)
PIN NAMES
A
0
− A
3
, B
0
− B
3
I
A = B
I
A < B
, I
A > B
O
A > B
O
A < B
O
A
= B
Parallel Inputs
A = B Expander Inputs
A < B, A > B, Expander Inputs
A Greater than B Output
B Greater than A Output
A Equal to B Output
HIGH
1.5 U.L.
1.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
LOW
0.75 U.L.
0.75 U.L.
0.25 U.L.
5 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA
HIGH/1.6 mA LOW.
LOGIC SYMBOL
10 12 13 15 9 11 14 1
4
2
3
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
I
A>B
O
A>B
I
A<B
O
A<B
I
A=B
O
A=B
V
CC
= PIN 16
GND = PIN 8
5
7
6
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2
SN74LS85
LOGIC DIAGRAM
(15)
(1)
A3
B3
(5)
(13)
O
A>B
(14)
(2)
A<B (3)
A=B (4)
A>B
A1
B1
(12)
(11)
A2
B2
(6)
O
A=B
(7)
O
A<B
A0
B0
(10)
(9)
TRUTH TABLE
COMPARING INPUTS
A
3
,B
3
A
3
>B
3
A
3
<B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
3
=B
3
A
2
,B
2
X
X
A
2
>B
2
A
2
<B
2
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
2
=B
2
A
1
,B
1
X
X
X
X
A
1
>B
1
A
1
<B
1
A
1
=B1
A
1
=B
1
A
1
=B
1
A
1
=B
1
A
1
=B
1
A
1
=B
1
A
1
=B
1
A
0
,B
0
X
X
X
X
X
X
A
0
>B
0
A
0
<B
0
A
0
=B
0
A
0
=B
0
A
0
=B
0
A
0
=B
0
A
0
=B
0
CASCADING
INPUTS
I
A>B
X
X
X
X
X
X
X
X
H
L
X
H
L
I
A<B
X
X
X
X
X
X
X
X
L
H
X
H
L
I
A=B
X
X
X
X
X
X
X
X
L
L
H
L
L
O
A>B
H
L
H
L
H
L
H
L
H
L
L
L
H
OUTPUTS
O
A<B
L
H
L
H
L
H
L
H
L
H
L
L
H
O
A=B
L
L
L
L
L
L
L
L
L
L
H
L
L
H = HIGH Level
L = LOW Level
X = IMMATERIAL
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3
SN74LS85
A n3
A n2
A n1
B n3
B n2
B n1
An
A
0
A
1
A
2
A
3
B
0
B
1
B
2
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
B
3
O
A > B
O
A < B
O
A = B
Bn
B
3
O
A > B
O
A < B
O
A = B
A
0
A
1
A
2
A
3
B
0
B
1
B
2
I
A > B
I
A < B
I
A = B
L
L
H
I
A > B
I
A < B
I
A = B
SN74LS85
SN74LS85
A>B
A<B
A=B
L = LOW LEVEL
H = HIGH LEVEL
Figure 1. Comparing Two n-Bit Words
APPLICATIONS
Figure 2 shows a high speed method of comparing two
24-bit words with only two levels of device delay. With the
technique shown in Figure 1, six levels of device delay result
Table 1
WORD LENGTH
1
−4
Bits
5
−24
Bits
25
−120
Bits
NUMBER OF PKGS.
1
2
−6
8
−31
when comparing two 24-bit words. The parallel technique
can be expanded to any number of bits, see Table 1.
NOTE:
The SN74LS85 can be used as a 5-bit comparator only
when the outputs are used to drive the A
0
−A
3
and B
0
−B
3
inputs of another SN74LS85 as shown in Figure 2 in posi-
tions #1, 2, 3, and 4.
INPUTS
(LSB)
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
I
A > B
O
A > B
I
A < B
#5
O
A < B
I
A = B
O
A = B
(MSB)
A
20
A
21
A
22
A
23
B
20
B
21
B
22
B
23
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
I
A > B
O
A > B
I
A < B
I
A = B
#1
O
A < B
O
A = B
NC
L
L
H
A
19
B
19
L
INPUTS
A
5
A
6
A
7
A
8
B
5
B
6
B
7
B
8
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
O
A > B
I
A > B
#4
I
A < B
O
A < B
I
A = B
O
A = B
NC
A
10
A
11
A
12
A
13
B
10
B
11
B
12
B
13
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
O
A > B
I
A > B
#3
I
A < B
O
A < B
I
A = B
O
A = B
NC
A
15
A
16
A
17
A
18
B
15
B
16
B
17
B
18
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
O
A > B
I
A > B
#2
I
A < B
O
A < B
I
A = B
O
A = B
NC
A
4
B
4
L
A
9
B
9
L
A
14
B
14
L
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
I
A > B
O
A > B
I
A < B
O
A < B
#6
I
A = B
O
A = B
OUTPUTS
MSB = MOST SIGNIFICANT BIT
LSB = LEAST SIGNIFICANT BIT
L = LOW LEVEL
H = HIGH LEVEL
NC = NO CONNECTION
Figure 2. Comparison of Two 24-Bit Words
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