1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM
Features
DDR2 SDRAM SOCDIMM
MT18HTS12872CH – 1GB
MT18HTS25672CH – 2GB
For component data sheets, refer to Micron’s Web site:
www.micron.com/products/ddr2sdram
Features
• 200-pin, small outline, dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, and
PC2-5300
• 1GB (128 Meg x 72), 2GB (256 Meg x 72)
• Supports ECC error detection and correction
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +3.0V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Phase-lock loop (PLL) to reduce system clock line
loading
• Gold edge contacts
• Dual rank
• I
2
C temperature sensor
Figure 1:
200-Pin SOCDIMM (MO-224 R/C “B”)
Height 30.0mm (1.18in)
Options
• Package
–
200-pin SODIMM (Pb-free)
• Frequency/CL
1
–
3.0ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-533)
–
5.0ns @ CL = 3 (DDR2-400)
• PCB height
–
30.0mm (1.18in)
Notes: 1. CL = CAS (READ) latency.
Marking
Y
-667
-53E
-40E
Table 1:
Address Table
1GB
2GB
8K
16K (A0–A13)
8 (BA0, BA1, BA2)
1KB
2Gb TwinDie (256 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
Refresh count
Row addressing
Device bank addressing
Device page size per bank
Device configuration
Column addressing
Module rank addressing
8K
16K (A0–A13)
4 (BA0, BA1)
1KB
1Gb TwinDie (128 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
PDF: 09005aef8253e3ea/ Source: 09005aef8253e404
HTS18C128_256x72CH.fm - Rev. A 9/06 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM
Features
Table 2:
Speed
Grade
-667
-53E
-40E
Key Timing Parameters
Data Rate (MT/s)
Industry Nomenclature
PC2-5300
PC2-4200
PC2-3200
CL = 5
667
–
–
CL = 4
533
533
400
CL = 3
400
400
400
t
RCD
(ns)
15
15
15
RP
(ns)
15
15
15
t
RC
(ns)
55
55
55
t
Table 3:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H128M8THK, 1Gb TwinDie™ DDR2 SDRAM
Module
Density
1GB
1GB
1GB
Configuration
128 Meg x 72
128 Meg x 72
128 Meg x 72
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
4-4-4
3-3-3
Part Number
1
MT18HTS12872CHY-667__
MT18HTS12872CHY-53E__
MT18HTS12872CHY-40E__
Table 4:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT47H256M8THJ, 2Gb TwinDie DDR2 SDRAM
Module
Density
2GB
2GB
2GB
Configuration
256 Meg x 72
256 Meg x 72
256 Meg x 72
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
4-4-4
3-3-3
Part Number
1
MT18HTS25672CHY-667__
MT18HTS25672CHY-53E__
MT18HTS25672CHY-40E__
Notes:
1. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT18HTS25672CHY-40EC2.
2. For the latest component data sheets, see Micron’s Web site:
www.micron.com/products/
ddr2sdram
PDF: 09005aef8253e3ea/ Source: 09005aef8253e404
HTS18C128_256x72CH.fm - Rev. A 9/06 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
200-Pin SODIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
V
REF
DQ0
Vss
DQ1
DQS0#
DQS0
Vss
DQ2
DQ3
Vss
DQ8
DQ9
Vss
DQS1#
DQS1
Vss
DQ10
DQ11
Vss
DQ16
DQ17
Vss
DQS2#
DQS2
Vss
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQ18
DQ19
Vss
DQ24
DQ25
Vss
DQS3#
DQS3
Vss
DQ26
DQ27
Vss
CB0
CB1
Vss
DQS8#
DQS8
Vss
CKE0
CKE1
EVENT#
V
DD
A12
A9
A7
Notes:
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
V
DD
A5
A3
A2
V
DD
A10
BA0
RAS#
V
DD
CAS#
S1#
V
DD
ODT1
NC
DQ32
V
SS
DQ33
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
DQ58
V
SS
DQ59
V
DDSPD
200-Pin SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
RESET#
DM2
Vss
DQ22
DQ23
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
V
SS
DQ28
DQ29
V
SS
DM3
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
V
SS
CB6
CB7
V
SS
CB2
CB3
V
SS
NC/BA2
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
A6
A4
V
DD
A1
A0
BA1
V
DD
WE#
S0#
ODT0
A13
V
DD
CK0
CK0#
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
V
SS
DM5
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
DQ62
V
SS
DQ63
SDA
SCL
SA1
SA0
94 NC/A14 144
96
A11
146
148
98
V
DD
100
A8
150
1. Pin 92 is NC for 1GB, BA2 for 2GB.
PDF: 09005aef8253e3ea/ Source: 09005aef8253e404
HTS18C128_256x72CH.fm - Rev. A 9/06 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM
Pin Assignments and Descriptions
Table 6:
Pin Descriptions
Refer to Table 5 for pin assignments
Symbol
ODT0, ODT1
Type
Input
Description
On-die termination:
ODT (registered HIGH) enables termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the
following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled
via the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK#.
Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is
enabled/disabled is dependent on the DDR2 SDRAM configuration and operating
mode. CKE LOW provides PRECHARGE power-down and SELF REFRESH operations
(all device banks idle), or ACTIVE power-down (row ACTIVE in any device bank). CKE
is synchronous for power-down entry, power-down exit, output disable, and for
SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers
(excluding CK, CK#, CKE, and ODT) are disabled during power-down . Input buffers
(excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will
detect a LVCMOS LOW level once V
DD
is applied during first power-up. After V
REF
has become stable during the power on and initialization sequence, it must be
maintained for proper operation of the CKE receiver. For proper SELF-REFRESH
operation V
REF
must be maintained to this input.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when S# is registered HIGH. S#
provides for external rank selection on systems with multiple ranks. S# is considered
part of the command code.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Bank address inputs:
BA0–BA1/BA2 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied BA0–BA1/BA2 define which mode
register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE
command.
Address inputs:
Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one device
bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10
HIGH). The address inputs also provide the op-code during a LOAD MODE
command.
Input data mask:
DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is
sampled on both edges of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
Data input/output:
Bidirectional data bus.
Check bits
Data strobe:
Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center aligned with write data. DQS# is
only used when differential data strobe mode is enabled via the LOAD MODE
command.
Temp sensor alarm output
Serial clock
for presence-detect: SCL is used to synchronize the presence-detect
data transfer to and from the module.
CK0, CK0#
Input
CKE0, CKE1
Input
S0#, S1#
Input
RAS#, CAS#, WE#
BA0, BA1
(1GB)
BA0, BA1, BA2
(2GB)
A0–A13
Input
Input
Input
DM0–DM8
Input
DQ0–DQ63
CB0–CB7
DQS0–DQS8,
DQS0#–DQS8#
I/O
I/O
I/O
EVENT#
SCL
Output
Input
PDF: 09005aef8253e3ea/ Source: 09005aef8253e404
HTS18C128_256x72CH.fm - Rev. A 9/06 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, DR): 200-Pin DDR2 SDRAM SOCDIMM
Pin Assignments and Descriptions
Table 6:
Pin Descriptions (Continued)
Refer to Table 5 for pin assignments
Symbol
SA0–SA1
SDA
V
DD
V
REF
V
SS
V
DDSPD
Type
Input
Input/
Output
Supply
Supply
Supply
Supply
Description
Presence-detect address inputs:
These pins are used to configure the presence-
detect device.
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses
and data into and out of the presence-detect portion of the module.
Power supply:
+1.8V ±0.1V.
SSTL_18 reference voltage
Ground
Serial EEPROM positive power supply:
+3.0V to +3.6V.
PDF: 09005aef8253e3ea/ Source: 09005aef8253e404
HTS18C128_256x72CH.fm - Rev. A 9/06 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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