256Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC66-, PC100-, and PC133-compliant
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web site:
www.micron.com/dramds
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x4 x8 x16
-
-
-
-
-
-
-
-
-
-
NC
NC
DQ0
NC NC
DQ0 DQ1
NC NC
NC
DQ2
NC NC
DQ1 DQ3
NC
V
DD
DQ0
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
VssQ
DQ7
V
DD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
x16 x8 x4
-
Vss
DQ15 DQ7
VssQ
-
DQ14
NC
DQ13 DQ6
V
DD
Q
-
DQ12
NC
DQ11 DQ5
VssQ
-
DQ10
NC
DQ9 DQ4
V
DD
Q
-
DQ8
NC
-
Vss
-
NC
DQMH DQM
-
CLK
CKE
-
A12
-
A11
-
A9
-
A8
-
A7
-
A6
-
A5
-
A4
-
Vss
-
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
-
NC
OPTIONS
• Configurations
64 Meg x 4
(16 Meg x 4 x 4 banks)
32 Meg x 8
( 8 Meg x 8 x 4 banks)
16 Meg x 16 ( 4 Meg x 16 x 4 banks)
• WRITE Recovery (
t
WR)
t
WR = “2 CLK”
1
MARKING
64M4
32M8
16M16
-
NC
-
NC
-
-
DQM
A2
• Package/Pinout
54-pin TSOP II OCPL
2
(400 mil)
60-ball FBGA (8mm x 16mm) (x4, x8)
54-ball FBGA (8mm x 14mm) (x16 only)
• Timing (Cycle Time)
7.5ns @ CL = 2 (PC133)
7.5ns @ CL = 3 (PC133)
• Self Refresh
Standard
Low power
• Operating Temperature
Commercial (0
o
C to +70
o
C)
Industrial (-40
o
C to +85
o
C)
NOTE:
1.
2.
3.
4.
5.
-
-
-
-
-
-
-
-
-
-
-
-
Note:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TG
FB
4, 5
FG
3
The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
-7E
-75
64 Meg x 4
32 Meg x 8
16 Meg x 16
Configuration
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
Refresh Count
8K
8K
8K
Row Addressing
8K (A0–A12)
8K (A0–A12)
8K (A0–A12)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
Column Addressing 2K (A0–A9, A11)
1K (A0–A9)
512 (A0–A8)
None
L
3
KEY TIMING PARAMETERS
SPEED
GRADE
-7E
-75
-7E
-75
CLOCK
ACCESS TIME
FREQUENCY CL = 2* CL = 3*
143 MHz
133 MHz
133 MHz
100 MHz
–
–
5.4ns
6ns
5.4ns
5.4ns
–
–
SETUP
TIME
1.5ns
1.5ns
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
None
IT
3
Refer to Micron Technical Note TN-48-05.
Off-center parting line.
Consult Micron for availability.
Not available in x16 configuration.
Actual FBGA part marking shown on page 58.
Part Number Example:
*CL = CAS (READ) latency
MT48LC16M16A2TG-75
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
256Mb: x4, x8, x16
SDRAM
60-BALL FBGA ASSIGNMENT
(Top View)
64 Meg x 4 SDRAM
8mm x 16mm “FB”
1
2
3
4
5
6
7
8
32 Meg x 8 SDRAM
8mm x 16mm “FB”
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
V
DD
Q
NC
NC
V
DD
Q
NC
NC
NC
NC
A12
A11
A8
A6
A4
Vss
VssQ
DQ3
NC
VssQ
DQ2
NC
Vss
DQM
CK
CKE
A9
A7
A5
Vss
V
DD
V
DD
Q
DQ0
NC
V
DD
Q
DQ1
NC
V
DD
WE#
RAS#
NC
BA1
A0
A2
V
DD
NC
NC
VssQ
NC
NC
VssQ
NC
NC
CAS#
NC
CS#
BA0
A10
A1
A3
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ7
NC
V
DD
Q
DQ5
NC
V
DD
Q
NC
NC
NC
NC
A12
A11
A8
A6
A4
Vss
VssQ
DQ6
NC
VssQ
DQ4
NC
Vss
DQM
CK
CKE
A9
A7
A5
Vss
V
DD
V
DD
Q
DQ1
NC
V
DD
Q
DQ3
NC
V
DD
WE#
RAS#
NC
BA1
A0
A2
V
DD
DQ0
NC
VssQ
DQ2
NC
VssQ
NC
NC
CAS#
NC
CS#
BA0
A10
A1
A3
Depopulated Balls
Depopulated Balls
NOTE:
FBGA pin Symbol, Type, and Descriptions are identical to the listing of the 54-pin TSOP table on page 9.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
54-BALL FBGA ASSIGNMENT
(Top View)
16 Meg x 16 SDRAM
8mm x 14mm “FG”
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
Vss
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
Vss
DQ15
DQ13
DQ11
DQ9
NC/SV
CLK
A11
A7
A5
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
Vss
CKE
A9
A6
A4
V
DD
Q
VssQ
V
DD
Q
V
SS
Q
V
DD
CAS#
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
LDQM
RAS#
BA1
A1
A2
V
DD
DQ1
DQ3
DQ5
DQ7
WE#
CS#
A10
V
DD
Depopulated Balls
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
256 Mb SDRAM PART NUMBERS
PART NUMBER
MT48LC64M4A2TG
MT48LC64M4A2FB*
MT48LC32M8A2TG
MT48LC32M8A2FB*
MT48LC16M16A2TG
MT48LC16M16A2FG
ARCHITECTURE
64 Meg x 4
64 Meg x 4
32 Meg x 8
32 Meg x 8
16 Meg x 16
16 Meg x 16
PACKAGE
54-pin TSOP II
60-ball FBGA
54-pin TSOP II
60-ball FBGA
54-pin TSOP II
54-ball FBGA
*Actual FBGA part marking shown on page 58.
GENERAL DESCRIPTION
The 256Mb SDRAM is a high-speed CMOS,
dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 67,108,864-bit banks is orga-
nized as 8,192 rows by 2,048 columns by
4 bits. Each of the x8’s 67,108,864-bit banks is orga-
nized as 8,192 rows by 1,024 columns by 8 bits. Each of
the x16’s 67,108,864-bit banks is organized as 8,192
rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank; A0–A12 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
The 256Mb SDRAM uses an internal pipelined ar-
chitecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V
memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All in-
puts and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
TABLE OF CONTENTS
Functional Block Diagram – 64 Meg x 4 .................... 6
Functional Block Diagram – 32 Meg x 8 .................... 7
Functional Block Diagram – 16 Meg x 16 .................. 8
Pin Descriptions .......................................................... 10
Ball Descriptions .......................................................... 10
Functional Description
...............................................
Initialization ...........................................................
Register Definition ................................................
Mode Register ...................................................
Burst Length ................................................
Burst Type ...................................................
CAS Latency ................................................
Operating Mode ..........................................
Write Burst Mode ........................................
Commands
...................................................................
Truth Table 1 (Commands and DQM Operation)
..............
Command Inhibit ..................................................
No Operation (NOP) ..............................................
Load mode register ................................................
Active .......................................................................
Read .......................................................................
Write .......................................................................
Precharge ................................................................
Auto Precharge .......................................................
Burst Terminate .....................................................
Auto Refresh ...........................................................
Self Refresh .............................................................
Operation
.....................................................................
Bank/Row Activation .............................................
Reads .......................................................................
Writes .......................................................................
Precharge ................................................................
Power-Down ...........................................................
Clock Suspend ........................................................
Burst Read/Single Write .......................................
12
12
12
12
12
13
14
14
14
15
15
16
16
16
16
16
16
16
16
17
17
17
18
18
19
25
27
27
28
28
Concurrent Auto Precharge .................................
Truth Table 2 (CKE)
......................................................
Truth Table 3 (Current State, Same Bank)
........................
Truth Table 4 (Current State, Different Bank)
..................
Absolute Maximum Ratings .......................................
DC Electrical Characteristics
and Operating Conditions .......................................
I
DD
Specifications and Conditions .............................
Capacitance ..................................................................
Electrical Characteristics
and Recommended AC Operating Conditions .......
Timing Waveforms
Initialize and Load mode register ........................
Power-Down Mode ................................................
Clock Suspend Mode ............................................
Auto Refresh Mode ................................................
Self Refresh Mode ..................................................
Reads
Read – Without Auto Precharge .....................
Read – With Auto Precharge ...........................
Single Read – Without Auto Precharge .........
Single Read – With Auto Precharge ...............
Alternating Bank Read Accesses ....................
Read – Full-Page Burst ....................................
Read – DQM Operation ...................................
Writes
Write – Without Auto Precharge .....................
Write – With Auto Precharge ...........................
Single Write - Without Auto Precharge .........
Single Write - With Auto Precharge ................
Alternating Bank Write Accesses ...................
Write – Full-Page Burst ....................................
Write – DQM Operation ...................................
29
31
32
34
36
36
36
37
37
AC Electrical Characteristics
(Timing Table) ......... 38
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
汽车电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
