4, 8, 16 MEG x 64
SDRAM SODIMMs
SMALL-OUTLINE
SDRAM MODULE
FEATURES
• JEDEC-standard 144-pin, small-outline, dual in-
line memory module (SODIMM)
• Utilizes 100 MHz and 125 MHz SDRAM compo-
nents
• Nonbuffered
• 32MB (4 Meg x 64), 64MB (8 Meg x 64) and 128MB
(16 Meg x 64)
• Single +3.3V
±0.3V
power supply
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode: Standard and Low Power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
MT4LSDT464(L)H, MT8LSDT864(L)H,
MT8LSDT1664(L)H
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Front View)
144-Pin Small-Outline DIMM (32MB)
OPTIONS
• Self Refresh Current
Standard
Low power
• Package
144-pin SODIMM (gold)
MARKING
None
L
G
• Frequency/CAS Latency
100 MHz/CL = 2 (8ns, 125 MHz SDRAMs)
100 MHz/CL = 3 (8ns, 125 MHz SDRAMs)
66 MHz/CL = 2 (10ns, 100 MHz SDRAMs)
-10E
-10C
-662
• Module Height
1.15" (32MB, 66 MHz, SS*)
-662_1
1.00" (32MB, 66 MHz, DS*)
-662_2
1.05" (64MB/128MB, 66 MHz, DS*)
-662_3
1.25" (32MB/64MB/128MB, 100 MHz, DS*) -10__5**
1.00" (32MB/64MB, 100 MHz, DS*)
-10__3**
* SS = Single Sided, DS = Double Sided.
** Adheres to PC100 SODIMM rev. 1.0 specification.
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
FRONT
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
V
SS
DQMB0
DQMB1
V
DD
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
DQ14
DQ15
V
SS
NC
NC
CK0
V
DD
RAS#
WE#
S0#
S1#
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
BACK
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
DQMB4
DQMB5
V
DD
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
DD
DQ44
DQ45
DQ46
DQ47
V
SS
NC
NC
CKE0
V
DD
CAS#
CKE1
RFU (A12)
RFU (A13)
PIN
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
FRONT
DNU
V
SS
NC
NC
V
DD
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
DD
A6
A8
V
SS
A9
A10
V
DD
DQMB2
DQMB3
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
SDA
V
DD
PIN
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
BACK
CK1
V
SS
NC
NC
V
DD
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
DQ53
DQ54
DQ55
V
DD
A7
BA0
V
SS
BA1
A11
V
DD
DQMB6
DQMB7
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
SCL
V
DD
NOTE:
Symbols in parentheses are not used on these modules but
may be used for other modules in this product family. They
are for reference only.
4, 8, 16 Meg x 64 SDRAM SODIMMs
ZM29.p65 – Rev. 9/99
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8, 16 MEG x 64
SDRAM SODIMMs
KEY SDRAM COMPONENT
TIMING PARAMETERS
MODULE
MARKING
-10E
-10C
-662
SPEED
GRADE
-8E
-8C
-10
CAS
ACCESS
LATENCY TIME
2
3
2
6ns
6ns
9ns
SETUP
TIME
2ns
2ns
2ns
HOLD
TIME
1ns
1ns
1ns
PART NUMBERS
PART NUMBER
MT4LSDT464HG-10E__
MT4LSDT464HG-10C__
MT4LSDT464HG-662__
MT4LSDT464LHG-10E__
MT4LSDT464LHG-10C__
MT4LSDT464LHG-662__
MT8LSDT864HG-10E__
MT8LSDT864HG-10C__
MT8LSDT864HG-662__
MT8LSDT864LHG-10E__
MT8LSDT864LHG-10C__
MT8LSDT864LHG-662__
MT8LSDT1664HG-10E__
MT8LSDT1664HG-10C__
MT8LSDT1664HG-662__
MT8LSDT1664LHG-10E__
MT8LSDT1664LHG-10C__
MT8LSDT1664LHG-662__
CONFIGURATION
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64*
4 Meg x 64*
4 Meg x 64*
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64*
8 Meg x 64*
8 Meg x 64*
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64*
16 Meg x 64*
16 Meg x 64*
VERSION
100 MHz, CL = 2
100 MHz, CL = 3
66 MHz, CL = 2
100 MHz, CL = 2
100 MHz, CL = 3
66 MHz, CL = 2
100 MHz, CL = 2
100 MHz, CL = 3
66 MHz, CL = 2
100 MHz, CL = 2
100 MHz, CL = 3
66 MHz, CL = 2
100 MHz, CL = 2
100 MHz, CL = 3
66 MHz, CL = 2
100 MHz, CL = 2
100 MHz, CL = 3
66 MHz, CL = 2
NOTE:
All part numbers end with a two-place code (not
shown), designating component and PCB revisions.
Consult factory for current revision codes. Example:
MT8LSDT864HG-10EB5.
*Low power option.
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are
used to select the bank and row to be accessed (BA0, BA1
select the bank, A0-A11 select the row). The address bits
registered coincident with the READ or WRITE com-
mand are used to select the starting column location for
the burst access.
These modules provide for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or the full
page, with a burst terminate option. An AUTO
PRECHARGE function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence. The modules use an internal pipelined
architecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while
accessing the alternate bank will hide the PRECHARGE
cycles and provide seamless, high-speed, random-ac-
cess operation.
The modules are designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs, outputs and clocks are LVTTL-compatible.
SDRAM modules offer substantial advances in
DRAM operating performance, including the ability to
synchronously burst data at a high data rate with
automatic column-address generation, the ability to
interleave between internal banks in order to hide
precharge time, and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 64Mb: x4, x8, x16 SDRAM data sheet.
GENERAL DESCRIPTION
The
MT4LSDT464(L)H, MT8LSDT864(L)H
and MT8LSDT1664(L)H are high-speed CMOS, dynamic
random-access, 32MB, 64MB and 128MB memories
organized in a x64 configuration. These modules use
SDRAMs that are internally configured as quad-bank
DRAMs with a synchronous interface (all signals are
registered on the positive edge of the clock signals CK0-
CK1). Read and write accesses to the SDRAM module are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
Micron
®
SERIAL PRESENCE-DETECT OPERATION
These modules incorporate serial presence-detect
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the cus-
tomer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM’s
SCL (clock) and SDA (data) signals.
4, 8, 16 Meg x 64 SDRAM SODIMMs
ZM29.p65 – Rev. 9/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
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