HY5V28(L)F
4Banks x 4M x 8bits Synchronous DRAM
DESCRIPTION
The Hynix HY5V28C(L)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applica-
tions which require large memory density and high bandwidth. HY5V28C(L)F is organized as 4banks of 4,194,304x8.
HY5V28C(L)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
•
•
•
Single 3.3±0.3V power supply
All device Balls are compatible with LVTTL interface
54Ball FBGA With 0.8mm of ball pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM
•
•
Internal four banks operation
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
ORDERING INFORMATION
Part No.
HY5V28CF-6
HY5V28CF-K
HY5V28CF-H
HY5V28CF-8
HY5V28CF-P
HY5V28CF-S
HY5V28CLF-6
HY5V28CLF-K
HY5V28CLF-H
HY5V28CLF-8
HY5V28CLF-P
HY5V28CLF-S
Clock Frequency
166MHz
133MHz
133MHz
Power
Organization
Interface
Package
Normal
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
Low power
125MHz
100MHz
100MHz
4Banks x 4Mbits
x8
LVTTL
54Ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1/Sep. 01
HY5V28C(L)F
Ball DESCRIPTION
Ball
CLK
Clock
Ball NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output Ball
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
CKE
CS
BA0, BA1
Clock Enable
Chip Select
Bank Address
A0 ~ A11
Address
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
RAS, CAS, WE
DQM
DQ0 ~ DQ7
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.1/Sep. 01
4
HY5V28C(L)F
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Ball relative to V
SS
Voltage on V
DD
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD,
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260
⋅
10
Rating
°C
°C
V
V
mA
W
°C ⋅
Sec
Unit
Note :
Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION
(T
A
=0 to 70°C)
Parameter
Power Supply Voltage
Input High voltage
Input Low voltage
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Min
3.0
2.0
-0.3
Typ
3.3
3.0
0
Max
3.6
V
DDQ
+ 0.3
0.8
Unit
V
V
V
Note
1
1,2
1,3
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.V
IL
(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION
(T
A
=0 to 70°C, V
DD
=3.3
±
0.3V, V
SS
=0V)
Parameter
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Symbol
V
IH
/ V
IL
Vtrip
tR / tF
Voutref
C
L
Value
2.4/0.4
1.4
1
1.4
50
Unit
V
V
ns
V
pF
1
Note
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 0.1/Sep.01
6
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