256Mb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
60-ball FBGA
(8mm X 14mm, 60 Ball)
FGL
•
ROHS Compliant
•
PC2100, PC2700, and PC3200 compatible
•
VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V (For –6A & -
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
75A)
VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (For -5B)
Bi-directional data strobe (DQS) transmitted/ received with
data, i.e. source-synchronous data capture (x16 has two: LDQS
and UDQS – one per byte)
Internal, pipelined double-data-rate (DDR) architecture; two
data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-aligned with
data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) for masking write data (x16 has two: LDM
and UDM – one per byte)
Programmable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh
Longer lead TSOP for improved reliability (OCPL)
2.5V I/O (SSTL_2 compatible)
These devices are optimized for single rank DIMM
applications.
Package Types (Leaded):
66-pin Plastic TSOP, OCPL
(400 mil width, 0.65mm pin pitch)
60-ball FBGA
(8mm X 14mm, 60 Ball)
TLF
FGF
Timing – Cycle Time:
5ns @ CL=3 (PC3200 or DDR400B)
6ns @ CL = 2.5 (PC2700 or DDR333)
7.5ns @ CL = 2.5 (PC2100 or DDR266)
Part number example:
-5B
-6A
-75A
SAA32M8T26AV8TLF-6A
(For part numbers prior to December
2004, refer to
page 12
for decoding, or for
part numbers prior to July 7
th
2006,
refer to
page 13
for decoding.)
Pin Assignment (Top View)
66 pin TSOP
Options:
Family:
SpecTek Memory
Designation:
SAA
64M4
32M8
16M16
Tx6x
Configuration:
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
Design ID:
DDR 256 Megabit Design
(Call SpecTek Sales for details on
availability of “x” placeholders)
Voltage and Refresh:
2.5V, Auto Refresh
2.5V, Self or Auto Refresh
V8
R8
TLL
Package Types (Lead-Free):
66-pin Plastic TSOP, OCPL
(400 mil width, 0.65mm pin pitch)
PDF: 09005aef8050fb60 / Source: 09005aef8050e4ee
256Mb: x4, x8, x16 DDR SDRAM
Rev: 07/17/2006
1
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2002, 2003, 2004 SpecTek
256Mb: x4, x8, x16
DDR SDRAM
GENERAL DESCRIPTION
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data rate
architecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n-prefetch architecture with
an interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the
256Mb DDR SDRAM effectively consists of a single 2n-bit
wide, one-clock-cycle data transfer at the internal DRAM
core and two corresponding
n-bit
wide, one-half-clock-cycle
data transfers at the I/O pins.
A bi-directional data strobe (DQS or LDQS/UDQS) is
transmitted externally, along with data, for use in data capture
at the receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller during
WRITEs. DQS is edge-aligned with data for READs and
center-aligned with data for WRITEs. The x16 offering has
two data strobes, one for the lower byte and one for the upper
byte.
The 256Mb DDR SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH and
CK# going LOW will be referred to as the positive edge of
CK. Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed. The address bits registered coincident with the
READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or
WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-timed
row precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-
saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All full drive strength outputs
are SSTL_2, Class II compatible.
NOTE 1:
The functionality and the timing specifications discussed
in this data sheet are for the DLL-enabled mode of
operation.
NOTE 2:
Throughout the data sheet, the various figures and text
refer to DQs as “DQ.” The DQ term is to be interpreted
as any and all DQ collectively, unless specifically stated
otherwise.
Additionally, the x16 is divided in to two bytes — the
lower byte and upper byte. For the lower byte (DQ0
through DQ7) DM refers to LDM and DQS refers to
LDQS; and for the upper byte (DQ8 through DQ15) DM
refers to UDM and DQS refers to UDQS.
________________________________________________________
ABSOLUTE MAXIMUM RATINGS*
(Voltages Relative to VSS)
VDD Supply
-1V to +3.6V
VDDQ Supply
-1V to +3.6V
VREF and Inputs
-1V to +3.6V
I/O Pins
-0.5V to VDDQ +0.5V
Operating Temperature, TA (ambient)
10°C to +70°C
Storage Temperature (plastic)
-55°C to +150°C
Power Dissipation
1W
Short Circuit Output Current
50mA
Disclaimer:
Except as specifically provided in this document, SpecTek makes
no warranties, expressed or implied, including, but not limited to, any
implied warranties of merchantability or fitness for a particular
purpose.
Any claim against SpecTek must be made within 1 year from the
date of shipment from SpecTek, and SpecTek has no liability
thereafter. Any liability is limited to replacement of the defective items
or return of amounts paid for defective items (at buyer’s election). In
no event will SpecTek be responsible for special, indirect,
consequential or incidental damages, even if SpecTek has been
advised for the possibility of such damages. SpecTek’s liability from
any cause pursuant to this specification shall be limited to general
monetary damages in an amount not to exceed the total purchase
price of the products covered by this specification, regardless of the
form in which legal or equitable action may be brought against
SpecTek.
PDF: 09005aef8050fb60 / Source: 09005aef8050e4ee
256Mb: x4, x8, x16 DDR SDRAM
Rev: 07/17/2006
2
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2002, 2003, 2004 SpecTek
256Mb: x4, x8, x16
DDR SDRAM
Ball assignment (Top View) 60 ball FBGA
PDF: 09005aef8050fb60 / Source: 09005aef8050e4ee
256Mb: x4, x8, x16 DDR SDRAM
Rev: 07/17/2006
3
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2002, 2003, 2004 SpecTek
256Mb: x4, x8, x16
DDR SDRAM
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(For test conditions, see note 53)
PARAMETER/CONDITION
Supply Voltage (For -6A & -75A)
I/O Supply Voltage (For -6A & -75A)
Supply Voltage (For -5B)
I/O Supply Voltage (For -5B)
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Clock Input Voltage Level; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
INPUT LEAKAGE CURRENT
Any input, 0V < VIN < VDD, VREF pin 0V < VIN < 1.35V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V < VOUT < VDDQ)
OUTPUT LEVELS:
Full drive option - x4 , x8, x16
High Current (VOUT = VDDQ-0.373V, minimum VREF,
minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
OUTPUT LEVELS: Reduced drive option - x16 only
High Current (VOUT = VDDQ-0.763V, minimum VREF,
minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)
SYMBOL
VDD
VDDQ
VDD
VDDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
V
ID
V
IX
I
I
MIN
2.3
2.3
2.5
2.5
0.49 X V
DDQ
V
REF
– 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
1.15
-2
MAX
2.7
2.7
2.7
2.7
0.51 X V
DDQ
V
REF
+ 0.04
V
DD
+ 0.3
V
REF
– 0.15
V
DDQ
+ 0.3
V
DDQ
+ 0.6
1.35
2
UNITS
V
V
V
V
V
V
V
V
V
V
V
µA
NOTES
41
41, 44
41
41, 44
6, 44
7, 44
28
28
8
9
I
OZ
I
OH
I
OL
-7
-16.8
16.8
7
--
--
µA
mA
mA
37, 39
I
OHR
I
OLR
-9
9
--
--
mA
mA
38, 39
AC INPUT OPERATING CONDITIONS
(For test conditions, see note 53)
PARAMETER/CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
I/O Reference Voltage
SYMBOL
V
IH
(
AC
)
V
IL
(
AC
)
V
ID
(
AC
)
V
IX
(
AC
)
V
REF
(
AC
)
MIN
V
REF
+ 0.310
--
0.7
0.5 X V
DDQ
– 0.2
0.49 X V
DDQ
MAX
--
V
REF
– 0.310
V
DDQ
+ 0.6
0.5 X V
DDQ
+ 0.2
0.51 X V
DDQ
UNITS
V
V
V
V
V
NOTES
14, 28, 40
14, 28, 40
8
9
6
CAPACITANCE (x4, x8)
(For test conditions, see note 53)
PARAMETER
Delta Input/Output Capacitance: DQs, DQS, DM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL
DC
IO
DC
I
1
DC
I
2
C
IO
C
I
1
C
I
2
C
I
3
MIN
--
--
--
4.0
2.0
2.0
2.0
MAX
0.50
0.50
0.25
5.0
3.0
3.0
3.0
UNITS
pF
pF
pF
pF
pF
pF
pF
NOTES
24
29
29
PDF: 09005aef8050fb60 / Source: 09005aef8050e4ee
256Mb: x4, x8, x16 DDR SDRAM
Rev: 07/17/2006
4
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2002, 2003, 2004 SpecTek
256Mb: x4, x8, x16
DDR SDRAM
I
DD
SPECIFICATIONS AND CONDITIONS (x4, x8)
(For test conditions, see note 53)
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); I
OUT
= 0mA; Address and control inputs changing
once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All
Standard
t
t
banks idle; Power-down mode; CK = CK(MIN); CKE=LOW;
‘V’ parts
Self Refresh
‘R’ parts
PRECHAGE FLOATING STANDBY CURRENT: CS# = HIGH; All banks idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control inputs changing once
per clock cycle. V
IN
= V
REF
for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down
mode;
t
CK =
t
CK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-
Precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs changing once per
clock cycle.
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle
t
AUTO REFRESH CURRENT
RC = tRFC (MIN)
SELF REFRESH CURRENT (Part number ‘R’ only)
OPERATING CURRENT: Four bank interleaving READs (BL = 4) with auto
precharge,
t
RC =
t
RC (MIN);
t
CK =
t
RC (MIN); Address and control inputs change
only during Active, READ, or WRITE commands.
SYMBO
L
I
DD
0
-5B
170
-6A
135
-75
110
UNITS
mA
NOTES
22, 48
I
DD
1
205
145
125
mA
22, 48
I
DD
2
P
I
DD
2
P
I
DD
2
F
10
4
60
10
3
50
10
3
45
mA
mA
mA
23, 32,
50
23, 32,
50
51
I
DD
3
P
I
DD
3
N
40
70
25
60
20
55
mA
mA
23, 32,
50
22
I
DD
4
R
275
190
115
mA
22, 48
I
DD
4
W
165
130
120
mA
22
I
DD
5
I
DD
6
I
DD
7
280
4
470
270
3
355
260
3
335
mA
mA
mA
22, 50
11
22, 49
PDF: 09005aef8050fb60 / Source: 09005aef8050e4ee
256Mb: x4, x8, x16 DDR SDRAM
Rev: 07/17/2006
5
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2002, 2003, 2004 SpecTek
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