®
256Mb: x4, x8, x16
DDR2 SDRAM
SAA64M4.....– 16 Meg x 4 x 4
SAA32M8.....– 8 Meg x 8 x 4
SAA16M16.....– 4 Meg x 16 x 4
For the latest data sheet, please refer to the SpecTek Web
site:
http://www.spectek.com
DDR2 SDRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ROHS compliant
V
DD
= +1.8V ±0.1V, V
DD
Q = +1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Programmable CAS Latency (CL): 3 and 4
Posted CAS additive latency (AL): 0, 1, 2, 3, and 4
WRITE latency = READ latency - 1
t
CK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Options
1, 2
• SpecTek Memory
• Configuration
64 Meg x 4 (16 Meg x 4 x 4)
32 Meg x 8 ( 8 Meg x 8 x 4)
16 Meg x 16 (4 Meg x 16 x 4)
• Product Code
DDR2
• Density
256 Megabits
• Voltage/Refresh
1.8V/8K refresh
• Package – Lead-Free
x4, x8
60-ball FBGA (8mm x 12mm)
x16
84-ball FBGA (8mm x 14mm)
• Package – Leaded
x4, x8
60-ball FBGA (8mm x 12mm)
x16
84-ball FBGA (8mm x 14mm)
• Timing – Cycle Time
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
NOTE:
Designation
SAA
Architecture
64 Meg x 4
16 Meg x 4 x 4
8K
8K (A0–A12)
4 (BA0–BA1)
2K (A0–A9, A11)
32 Meg x 8
8 Meg x 8 x 4
8K
8K (A0–A12)
4 (BA0–BA1)
1K (A0–A9)
16 Meg x 16
4 Meg x 16 x 4
8K
8K (A0–A12)
4 (BA0–BA1)
512 (A0–A8)
64M4
32M8
16M16
Ux
3
6x
3
O8
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column
Addressing
Table 1:
Speed
Grade
-3
-37E
Key Timing Parameters
Data Rate (MHz)
CL = 4
NA
533
CL = 5
667
533
t
RCD
t
RP
t
Rc
FIF
FPF
(ns)
15
15
(ns)
15
15
(ns)
60
60
FIL
Part Number Example:
FPL
-3
-37E
SAA32M8U26AO8FIF-37E
1. See page 42 for part number options and desig-
nations used prior to March 2005.
2. See page 42 for part number options and desig-
nations used prior to July 2006.
3. Contact SpecTek Sales for details on availability
of the "x" placeholders
PDF: 09005aef81548c1c/Source: 09005aef819e80c5
SpecTek_DDR2_256Mb_1.fm - Rev. C 7/06 EN
1
SpecTek reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
®
256Mb: x4, x8, x16
DDR2 SDRAM
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Input Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Input Slew Rate Derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Data Slew Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Power and Ground Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Output Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Full Strength Pull-Down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Full Strength Pull-Up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
FBGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
I
DD
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
I
DD
7 Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Part Number Options and Designations Prior to March 2005. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Part Number Options and Designations Prior to July 2006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
PDF: 09005aef81548c1c/Source: 09005aef819e80c5
SpecTek_DDR2_256MbTOC.fm - Rev. C 7/06 EN
2
SpecTek reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
®
256Mb: x4, x8, x16
DDR2 SDRAM
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
84-ball FBGA Pin Assignment (x16), 8mm x 14mm (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
60-Ball FBGA Pin Assignment (x 4, x 8), 8mm x 12mm (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Functional Block Diagram (64 Meg x 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Block Diagram (32 Meg x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Functional Block Diagram (16 Meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Single-Ended Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Differential Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Nominal Slew Rate for
t
IS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Tangent Line for
t
IS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Nominal Slew Rate for
t
IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Tangent Line for
t
IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Nominal Slew Rate for
t
DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Tangent Line for
t
DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Nominal Slew Rate for
t
DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Tangent Line for
t
DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
AC Input Test Signal Waveform Command/Address pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
AC Input Test Signal Waveform for Data with DQS,DQS# (differential) . . . . . . . . . . . . . . . . . . . . . . . .23
AC Input Test Signal Waveform for Data with DQS (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
AC Input Test Signal Waveform (differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Differential Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Output Slew Rate Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Full Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Full Strength Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Package Drawing 60-Ball (8mm x 12mm) FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Package Drawing 84-Ball (8mm x 14mm) FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
PDF: 09005aef81548c1c/Source: 09005aef819e80c5
SpecTek_DDR2_256MbLOF.fm - Rev. C 7/06 EN
3
SpecTek reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
®
256Mb: x4, x8, x16
DDR2 SDRAM
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Recommended DC Operating Conditions (SSTL_18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Input DC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Differential Input Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Setup and Hold Time Derating Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
t
DS,
t
DH Derating Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Clock, Data, Strobe, and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Differential AC Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Output Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Pulldown Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
DDR2 I
DD
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
General I
DD
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
I
DD
7 Timing Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PDF: 09005aef81548c1c/Source: 09005aef819e80c5
SpecTek_DDR2_256MbLOT.fm - Rev. C 7/06 EN
4
SpecTek reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
®
256Mb: x4, x8, x16
DDR2 SDRAM
Read and write accesses to the DDR2 SDRAM are
burst-oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed.
The address bits registered coincident with the READ
or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read
or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight
with another read, or a burst write of eight with
another write. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst access.
As with standard DDR SDRAMs, the pipelined,
multibank architecture of DDR2 SDRAMs allows for
concurrent operation, thereby providing high, effec-
tive bandwidth by hiding row precharge and activation
time.
A self refresh mode is provided, along with a power-
saving power-down mode.
All inputs are compatible with the JEDEC standard
for SSTL_18. All full drive-strength outputs are
SSTL_18-compatible.
NOTE: 1. The functionality and the timing specifica-
tions discussed in this data sheet are for the
DLL-enabled mode of operation.
2. Throughout the data sheet, the various fig-
ures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ
collectively, unless specifically stated other-
wise. Additionally, the x16 is divided into
two bytes, the lower byte and upper byte.
For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS. For
the upper byte (DQ8 through DQ15) DM
refers to UDM and DQS refers to UDQS.
3. Complete functionality is described
throughout the document and any page or
diagram may have been simplified to con-
vey a topic and may not be inclusive of all
requirements.
4. Any specific requirement takes precedence
over a general statement.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged compo-
nents have an abbreviated part marking that is differ-
ent from the part number. SpecTek’s new FBGA part
marking decoder makes it easier to understand FBGA
part marking. Visit the SpecTek web site at
www.spec-
tek.com/pdfs/fbga_decoder.pdf
.
General Description
The 256Mb DDR2 SDRAM is a high-speed, CMOS
dynamic
random-access
memory
containing
268,435,456 bits. It is internally configured as a quad-
bank DRAM. The functional block diagrams of the 16
Meg x 16, 32 Meg x 8, and 64 Meg x 4 devices, respec-
tively are shown in the Functional Description section.
Ball assignments for the 64 Meg x 4 are shown in
Figure 1 and signal descriptions are shown in Table 1.
Ball assignments for the 32 Meg x 8 and 64 Meg x 4 are
shown in Figure 2 and signal descriptions are shown in
Table 2.
The 256Mb DDR2 SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 4n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 256Mb DDR2
SDRAM effectively consists of a single 4n-bit-wide,
one-clock-cycle data transfer at the internal DRAM
core and four corresponding
n-bit-wide,
one-half-
clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmit-
ted externally, along with data, for use in data capture
at the receiver. DQS is a strobe transmitted by the
DDR2 SDRAM during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data
for READs and center-aligned with data for WRITEs.
The x16 offering has two data strobes, one for the
lower byte (LDQS, LDQS#) and one for the upper byte
(UDQS, UDQS#).
The 256Mb DDR2 SDRAM operates from a differen-
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
PDF: 09005aef81548c1c/Source: 09005aef819e80c5
SpecTek_DDR2_256Mb_2.fm - Rev. C 7/06 EN
5
SpecTek reserves the right to change products or specifications without notice.
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