These specs apply over the rated power supply, temperature,and reference frequency ranges; 10% signal amplitude variation, and 10% harmonic distortion.
PARAMETER
RESOLUTION
FREQUENCY RANGE
ACCURACY -XX2
(Note 3)
-XX3
(Note 3)
Repeatability
Differential Linearity
FREQUENCY RANGE
ACCURACY -XX5
(Note 3)
Repeatability
Differential Linearity
REFERENCE
Type
Voltage: differential
single ended
overload
Frequency
Input Impedance
Common Mode Range
SYNTHESIZED REFERENCE
±Sig/Ref Phase Shift Correction
SIGNAL INPUT
Type
Voltage: operating
overload
Input impedance
DIGITAL INPUTS (Note 10)
TTL / CMOS COMPATIBLE INPUTS
Inhibit (INH)
Enable Bits 1 to 8 (EM) }
Enable Bits 9 to 16 (EL) }
Resolution and Mode Control (D1 & D0)
(See Notes 1 & 2)
UNIT
Bits
Hz
minutes
minutes
LSB
LSB
Hz
minutes
LSB
LSB
VALUE
10, 12, 14, or 16 (Note 1 & 2)
1k - 4k
4 +1 LSB
2 +1 LSB
±1
±1
1k - 5k (Note 12)
1 +1 LSB
±1
±1
Vp-p
Vp
Vp
Hz
Ω
Vp
deg
Vrms
Vp
Ω
47-1k (Note 4)
4 +1 LSB
2 +1 LSB
±1
±1
47-1k (Note 4)
1 +1 LSB
±1
±1
(+RH, -RL)
Differential
10 max. (Note 11)
±5 max. (1.5 min.)(Note 11)
±25 continuous; ±100 transient
DC to 10k (Note 12)
10M minutes. || 20 pf
3
(note 5)
45 max. from 400 Hz to 10kHz
(+S, -S, SIN, +C, -C, COS)
Resolver, differential, groundbased
2 ±15%
±25 continuous
10M minutes || 10 pF.
4k - 10k
5 +1 LSB
3 +1 LSB
±2
±2
Logic 0 = 0.8 V max. / Logic 1 = 2.0 V minutes.
Loading=10 µA max P.U. current source to +5 V || 5 pF max., CMOS transient protected
Logic 0 inhibits; Data stable within 150 ns (Logic 1 = Transparent)
{ Logic 0 enables; Data stable within 150 ns (Logic 0 = Transparent)
{ Logic 1 = High Impedance; Data High Z within 100 ns (Note 8)
Mode
Resolver
“
“
“
LVDT
“
“
“
D1
0
0
1
1
-5 V
0
1
-5 V
D0
0
1
0
1
0
-5 V
-5 V
-5 V
Resolution
10 bits
12 bits
14 bits
16 bits (Preset, Note 10)
8 bits
10 bits
12 bits
14 bits
ZIP_EN
CMOS Compatible Inputs
SHIFT
Notes:
Logic 0 enables ZIP, Logic 1 enables CB
Logic 0 = 1.5 V max., Logic 1 = 3.5 V minutes., negative voltage = -3.5 V minutes.
1. As parallel resolution is reduced, pairs of bits are disabled. (Unused bits are set to a logic “0.”)
• 14 bit resolution: 15/16 disabled, • 12 bit resolution: 13/14, 15/16 disabled, • 10 bit resolution: 11/12, 13/14, 15/16 disabled
2. In LVDT mode, Bit 3 is the MSB and resolution is programmable to 8, 10, 12, and 14 bits.
3. Accuracy specification below for LVDT mode, null to + full scale travel (45 degrees) (2-wire configuration).
4 Minute part = 0.15% + 1 LSB of full scale “resolution set”
2 Minute part = 0.07% + 1 LSB of full scale “resolution set”
1 Minute part = 0.035% + 1 LSB of full scale “resolution set”
Accuracy specification below for LVDT mode, full scale travel (90 degrees) (3-wire configuration).
4 Minute part = 0.07% + 1 LSB of full scale “resolution set”
2 Minute part = 0.035% + 1 LSB of full scale “resolution set”
1 Minute part = 0.017% + 1 LSB of full scale “resolution set”
Note that these accuracy specifications are for the converter and do not consider any front end external resistor tolerances.
4. In the frequency range of 47Hz to 1kHz, there will be 1 LSB of jitter at quadrant boundaries.
5. The maximum phase shift tolerance will degrade linearly from 45 degrees at 400 Hz to 30 degrees at 60 Hz.
6. When using the -5V inverter, the VDD supply current will double and VSSP can be up to 20% low, or -4V.
7. || = in parallel with.
8. High Z refers to parallel data only.
9. Normal ESD (Electro Static Device) handling precautions should be observed.
10. Any unused pins may be left floating (unconnected). All TTL & CMOS input pins are internally pulled up to +5 Volts.
11. A signal less than 500 mV will assert BIT.
12. -XX5 accuracy is 1 minute + 1 LSB up to 5 kHz max.
13. For Ka definition, see the RDC-19220/RD-19230 application manual acceleration lag section.
Data Device Corporation
www.ddc-web.com
3
RD-19230
P-05/05-0
TABLE 1. RD-19230 SPECIFICATIONS (CONTINUED)
These specs apply over the rated power supply, temperature, and reference frequency ranges; 10% signal amplitude variation, and 10% harmonic distortion.
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