HD74LS123
Dual Retriggerable Monostable Multivibrators (with Clear)
REJ03D0429–0200
Rev.2.00
Feb.18.2005
This d-c triggered multivibrator features output pulse width control by three method. The basic pulse time is
programmed by selection of external resistance and capacitance values. Once triggered, the basic pulse width may be
extended by retriggering the gated low-level -active (A) or high-level active (B) inputs, or be reduced by use of the
overriding clear. Figure 1 illustrates pulse control by retriggering and early clear. This device is provided enough
Schmitt hysteresis to ensure jitter-free triggering from the B input with transition rates as slow as 0.1 mV/ns.
Features
•
Ordering Information
Part Name
HD74LS123P
HD74LS123FPEL
HD74LS123RPEL
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
SOP-16 pin (JEDEC)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
Package
Abbreviation
P
FP
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
PRSP0016DG-A
RP
(FP-16DNV)
Note: Please consult the sales office for the above package availability.
A = "L"
Clear = "H"
B
Retrigger Pulse
"H"
"L"
t
w
+ t
PLH
"H"
Q
t
w
Output without
retrigger
A = "L"
"H"
"L"
B
"L"
"H"
Clear
"L"
"H"
Q
"L"
Output without
clear
Figure 1
Typical Input / Output Pulse
Rev.2.00, Feb.18.2005, page 1 of 8
HD74LS123
Pin Arrangement
1A
1B
1CLR
1Q
2Q
2Cext
2Rext/Cext
GND
1
2
3
4
5
Q
6
7
8
Q
CLR
CLR
Q
16
15
14
Q
13
12
11
10
9
V
CC
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
2A
(Top view)
Function Table
Inputs
Clear
A
1
L
X
X
H
X
X
H
L
H
↓
↑
L
Notes: H; high level, L; low level, X; irrelevant
↑;
transition from low to high level
↓;
transition from high to low level
; one high-level pulse
; one low-level pulse
Outputs
B
2
X
X
L
↑
H
H
Q
L
L
L
Q
H
H
H
Block Diagram (1/2)
External parameter
Cext
A
B
Rext
/Cext
V
CC
Q
Q
Q
Clear
Clear
Q
Rev.2.00, Feb.18.2005, page 2 of 8
HD74LS123
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
P
T
Tstg
Ratings
7
7
400
–65 to +150
Unit
V
V
mW
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Input pulse width
External timing resistance
External capacitance
Wiring capacitance at Rext/Cext terminal
A, B
CLR
“H”
“L”
“L”
R
ext
C
ext
—
t
w (in)
Symbol
V
CC
I
OH
I
OL
Topr
Min
4.75
—
—
–20
40
40
40
5
Typ
5.00
—
—
25
—
—
—
—
Non restriction
—
50
pF
Max
5.25
–400
8
75
—
—
—
260
Unit
V
µA
mA
°C
ns
ns
ns
kΩ
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
V
IH
V
IL
V
OH
Output voltage
V
OL
I
IH
I
IL
I
I
Short-circuit output
current
Supply current**
Input clamp voltage
I
OS
I
CC
V
IK
min.
2.0
—
2.7
—
—
—
—
—
–20
—
—
typ.*
—
—
—
—
—
—
—
—
—
12
—
max.
—
0.8
—
0.4
0.5
20
–0.4
0.1
–100
20
–1.5
Unit
V
V
V
V
µA
mA
mA
mA
mA
V
Condition
V
CC
= 4.75 V, V
IH
= 2 V, V
IL
= 0.8 V,
I
OH
= –400
µA
I
OL
= 4 mA
V
CC
= 4.75 V, V
IH
= 2 V,
V
IL
= 0.8 V
I
OL
= 8 mA
V
CC
= 5.25 V, V
I
= 2.7 V
V
CC
= 5.25 V, V
I
= 0.4 V
V
CC
= 5.25 V, V
I
= 7 V
V
CC
= 5.25 V
V
CC
= 5.25 V
V
CC
= 4.75 V, I
IN
= –18 mA
Input current
* V
CC
= 5 V, Ta = 25
°
C
** With all outputs open and 4.5 V applied to all data and clear inputs, I
CC
is measured after a momentary ground, then
4.5 V, is applied to clock.
Note: To measure V
OH
at Q, V
OL
at
Q,
or I
OS
at Q, ground R
ext
/ C
ext
, apply 2 V to B and clear, and pulse A from
2 V to 0 V.
Rev.2.00, Feb.18.2005, page 3 of 8
HD74LS123
Switching Characteristics
(V
CC
= 5 V, Ta = 25°C)
Item
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
(out)min
Output pulse width
t
(out)
A, B
Inputs
A
B
CLR
Outputs
Q
Q
Q
Q
Q
Q
Q
Q
min.
—
—
—
—
—
—
—
4
typ.
23
32
23
34
20
28
116
4.5
max.
33
45
44
56
27
45
200
5
Unit
Condition
Propagation delay
time
ns
C
ext
= 0, R
ext
= 5 kΩ,
C
L
= 15 pF, R
L
= 2 kΩ
µs
C
ext
= 1000 pF,
R
ext
= 10 kΩ,
C
L
= 15 pF, R
L
= 2 kΩ
Typical Application Data for HD74LS123
For pulse widths when C
ext
≤
1000 pF, See Figure 3.
The output pulse is primarily a function of the external capacitor and resistor. For C
ext
> 1000 pF, the output pulse
width (t
w
) is defined as: t
w(out)
= K
•
R
ext
•
C
ext
; See Figure 4.
V
CC
Rext
+
–
Cext
Rext (kΩ)
Cext (pF)
t
w(out)
(ns)
to Cext
to Rext/Cext
Figure 2
Timing Component Connections
100,000
Output pulse width t
w
(ns)
Rext = 160kΩ
10,000
1,000
Rext = 80kΩ
40kΩ
20kΩ
10kΩ
5kΩ
100
10
1
10
100
1,000
External capacitance Cext (pF)
Figure 3
Typical Output Pulse Width (Cext
≤
1000 pF)
Rev.2.00, Feb.18.2005, page 4 of 8
HD74LS123
0.5
A coefficient of output pulse width K
0.4
0.3
0.2
0.1
0
V
CC
= 5V
Ta = 25°C
10
3
2 3
5 710
4
2 3
5 710
5
2 3
5 710
6
2 3
5 710
7
Timing capacitance Cext (pF)
Figure 4
C
ext
vs. K (C
ext
> 1000 pF)
Rev.2.00, Feb.18.2005, page 5 of 8
stm32/stm8
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