Philips Semiconductors
Product data
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ABT16821A
74ABTH16821A
FEATURES
•
20-bit positive-edge triggered register
•
Multiple V
CC
and GND pins minimize switching noise
•
Live insertion/extraction permitted
•
Power-up reset
•
Power-up 3-State
•
74ABTH16821A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
DESCRIPTION
The 74ABT16821A high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16821A has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW Output Enable (nOE) controls all ten 3-State
buffers independent of the register operation. When nOE is LOW,
the data in the register appears at the outputs. When nOE is HIGH,
the outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
Two options are available, 74ABT16821A which does not have the
bus-hold feature and 74ABTH16821A which incorporates the
bus-hold feature.
•
Output capability: +64 mA / –32 mA
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
I
CCL
PARAMETER
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Quiescent supply current
CONDITIONS
T
amb
= 25
°C;
GND = 0 V
C
L
= 50 pF; V
CC
= 5 V
V
I
= 0 V or V
CC
V
O
= 0 V or V
CC
; 3-State
Outputs disabled; V
CC
= 5.5 V
Outputs LOW; V
CC
= 5.5 V
TYPICAL
2.4
2.0
3
7
500
10
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
–40
°C
to +85
°C
PART NUMBER
74ABT16821ADL
74ABT16821ADGG
74ABTH16821ADGG
DWG NUMBER
SOT371-1
SOT364-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 28
56, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1D0 – 1D9
2D0 – 2D9
1Q0 – 1Q9
2Q0 – 2Q9
1OE, 2OE
1CP, 2CP
GND
V
CC
Data inputs
Data outputs
Output enable inputs (active-LOW)
Clock pulse inputs (active rising edge)
Ground (0 V)
Positive supply voltage
FUNCTION
2002 Dec 13
2
Philips Semiconductors
Product data
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ABT16821A
74ABTH16821A
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
D
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
SH00004
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output
voltage
3
V
O
< 0 V
Output in Off or HIGH state
Output in LOW state
Output in HIGH state
V
I
< 0 V
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–64
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
DC output current
out ut
Storage temperature range
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
PARAMETER
MIN
4.5
0
2.0
0.8
–32
64
10
+85
LIMITS
MAX
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
2002 Dec 13
4
Philips Semiconductors
Product data
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ABT16821A
74ABTH16821A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
°C
Min
V
IK
V
OH
V
OL
V
RST
I
I
I
I
Input clamp voltage
V
CC
= 4.5 V; I
IK
= –18 mA
V
CC
= 4.5 V; I
OH
= –3 mA; V
I
= V
IL
or V
IH
HIGH-level output voltage
V
CC
= 5.0 V; I
OH
= –3 mA; V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
= –32 mA; V
I
= V
IL
or V
IH
LOW-level output voltage
Power-up output voltage
3
Input leakage current
Input leakage current
74ABTH16821A
V
CC
= 4.5 V; I
OL
= 64 mA; V
I
= V
IL
or V
IH
V
CC
= 5.5 V; I
O
= 1 mA; V
I
= GND or V
CC
V
CC
= 5.5 V; V
I
= V
CC
or GND
V
CC
= 5.5 V; V
I
= V
CC
or GND
V
CC
= 5.5 V; V
I
= V
CC
V
CC
= 5.5 V; V
I
= 0
V
CC
= 4.5 V; V
I
= 0.8 V
I
HOLD
Bus Hold current
74ABTH16821A
inputs
5
V
CC
= 4.5 V; V
I
= 2.0 V
V
CC
= 5.5 V; V
I
= 0 to 5.5 V
I
OFF
I
PU/PD
I
OZH
I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current
per input pin
2
Quiescent supply current
Power-off leakage current
Power-up/down 3-State
output current
4
3-State output HIGH current
3-State output LOW current
Output HIGH leakage
current
Output current
1
V
CC
= 0.0 V; V
O
or V
I
≤
4.5 V
V
CC
= 2.1 V; V
O
= 0.5 V; V
I
= GND or V
CC
;
V
OE
= Don’t care
V
CC
= 5.5 V; V
O
= 2.7 V; V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
O
= 0.5 V; V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
O
= 5.5 V; V
I
= GND or V
CC
V
CC
= 5.5 V; V
O
= 2.5 V
V
CC
= 5.5 V; Outputs HIGH, V
I
= GND or V
CC
V
CC
= 5.5 V; Outputs LOW, V
I
= GND or V
CC
V
CC
= 5.5 V; Outputs 3-State; V
I
= GND or V
CC
V
CC
= 5.5 V; one input at 3.4 V, other inputs at
V
CC
or GND
–50
Control pins
Data pins
35
–75
±800
±5.0
±5.0
1.0
–1.0
5.0
–90
0.5
10
0.5
0.25
±100
±50
10
–10
50
–180
1
19
1
1.5
–50
±100
±50
10
–10
50
–180
1
19
1
1.5
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
2.5
3.0
2.0
Typ
–0.9
2.9
3.4
2.4
0.36
0.13
±0.01
±0.01
0.01
–1
0.55
0.55
±1.0
±1
1
–3
35
–75
µA
Max
–1.2
2.5
3.0
2.0
0.55
0.55
±1.0
±1
1
–5
T
amb
= –40
°C
to +85
°C
Min
Max
–1.2
V
V
V
V
V
V
µA
µA
µA
µA
UNIT
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0 V and 2.1 V with a transition time of up to 10 msec. From V
CC
= 2.1 V to V
CC
= 5 V a
transition time of up to 100
µsec
is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
2002 Dec 13
5
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