ADVANCE
32, 64 MEG x 72
REGISTERED FBGA SDRAM DIMM
SYNCHRONOUS
DRAM MODULE
FEATURES
• JEDEC-standard 168-pin, dual in-line memory module
(DIMM)
• PC100 and PC133**-compliant
• Uses FBGA-packaged SDRAM components
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Utilizes 125 MHz and 133 MHz SDRAM components
• ECC-optimized pinout
• 256MB (32 Meg x 72) and 512MB (64 Meg x 72)
• Single +3.3V
±0.3V
power supply
• Fully synchronous; all signals registered on positive
edge of PLL clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
MT36LSDF3272, MT36LSDF6472
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Front View)
168-Pin DIMM
OPTIONS
• Package
168-pin DIMM (gold)
MARKING
G
• Frequency/CAS Latency*
133 MHz/CL = 3 (7.5ns, 133 MHz SDRAMs)-133**
100 MHz/CL = 2 (8ns, 125 MHz SDRAMs) -10E
* Device latency only; extra clock cycle required due to input register.
**Please contact factory for availability.
KEY SDRAM COMPONENT
TIMING PARAMETERS
MODULE
MARKING
-133
-10E
SPEED
GRADE
-75
-8E
ACCESS
TIME
6ns
6ns
SETUP
TIME
1.5ns
2ns
HOLD
TIME
0.8ns
1ns
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
SYMBOL
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
S0#
DNU
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
PIN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
SYMBOL
V
SS
DNU
S2#
DQMB2
DQMB3
DNU
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC (CKE1)
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
DD
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
DD
CAS#
DQMB4
DQMB5
S1#
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CK1
NC (A12)
PIN
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
V
SS
CKE0
S3#
DQMB6
DQMB7
NC (A13)
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
NOTE:
Symbols in parentheses are not used on these modules but may be used
for other modules in this product family. They are for reference only.
32, 64 Meg x 72 Registered FBGA SDRAM DIMM
ZM32.p65 – Rev. 6/99
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
Micron is a registered trademark of Micron Technology, Inc.
ADVANCE
32, 64 MEG x 72
REGISTERED FBGA SDRAM DIMM
PART NUMBERS
PART NUMBER
CONFIGURATION SYSTEM BUS SPEED
MT36LSDF3272G-133__
32 Meg x 72
133 MHz
MT36LSDF3272G-10E__
32 Meg x 72
100 MHz
*MT36LSDF6472G-133__ 64 Meg x 72
133 MHz
*MT36LSDF6472G-10E__ 64 Meg x 72
100 MHz
NOTE:
All part numbers end with a two-place code (not shown),
designating component and PCB revisions. Consult
factory for current revision codes. Example:
MT36LSDF3272G-10EB1
* Please contact factory for availability.
GENERAL DESCRIPTION
The MT36LSDF3272 and MT36LSDF6472 are high-speed
CMOS, dynamic random-access, 256MB and 512MB memo-
ries organized in a x72 configuration. These modules use
internally configured quad-bank SDRAMs with a synchro-
nous interface (all signals are registered on the positive
edge of clock signal CK0).
Read and write accesses to the SDRAM modules are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0, BA1 select the bank, A0-A11 select
the row). The address bits registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
These modules provide for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or full page,
with a burst terminate option. An AUTO PRECHARGE
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst sequence.
The modules use an internal pipelined architecture to
achieve high-speed operation. This architecture is compat-
ible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the PRECHARGE cycles and provide seam-
less, high-speed, random-access operation.
These modules are designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM
operating performance, including the ability to syn-
chronously burst data at a high data rate with automatic
column-address generation, the ability to interleave be-
tween internal banks in order to hide precharge time, and
the capability to randomly change column addresses on
each clock cycle during a burst access. For more informa-
tion regarding SDRAM operation, refer to the 64Mb: x4, x8,
x16 or the 128Mb: x4, x8, x16 SDRAM data sheets.
PLL AND REGISTER OPERATION
These modules can be operated in either registered mode
(REGE pin HIGH), where the control/address input signals
are latched in the register on one rising clock edge and sent
to the SDRAM devices on the following rising clock edge
(data access is delayed by one clock), or in buffered mode
(REGE pin LOW) where the input signals pass through the
register/buffer to the SDRAM devices on the same clock. A
phase-lock loop (PLL) on the modules is used to redrive the
clock signals to the SDRAM devices to minimize system
clock loading (CK0 is connected to the PLL, and CK1, CK2
and CK3 are terminated).
SERIAL PRESENCE-DETECT OPERATION
These modules incorporate serial presence-detect (SPD).
The SPD function is implemented using a 2,048-bit EEPROM.
This nonvolatile storage device contains 256 bytes. The first
128 bytes can be programmed by Micron to identify the
module type and various SDRAM organizations and tim-
ing parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/WRITE
operations between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
32, 64 Meg x 72 Registered FBGA SDRAM DIMM
ZM32.p65 – Rev. 6/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
ADVANCE
32, 64 MEG x 72
REGISTERED FBGA SDRAM DIMM
FUNCTIONAL BLOCK DIAGRAM
MT36LSDF3272 (256MB)/MT36LSDF6472 (512MB)
RS1#
RS0#
RDQMB0
DQ0
DQ1
DQ2
DQ3
DQM CS#
DQ0
DQ1 U0
DQ2
DQ3
DQM CS#
DQ0
DQ1 U1
DQ2
DQ3
DQM CS#
DQ0
DQ1 U9
DQ2
DQ3
DQM CS#
DQ0
DQ1 U10
DQ2
DQ3
RDQMB4
DQ32
DQ33
DQ34
DQ35
DQM CS#
DQ0
DQ1 U18
DQ2
DQ3
DQM CS#
DQ0
DQ1 U19
DQ2
DQ3
DQM CS#
DQ0
DQ1 U27
DQ2
DQ3
DQM CS#
DQ0
DQ1 U28
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RDQMB1
DQ8
DQ9
DQ10
DQ11
DQ36
DQ37
DQ38
DQ39
RDQMB5
DQM CS#
DQ0
DQ1 U2
DQ2
DQ3
DQM CS#
DQ0
DQ1 U11
DQ2
DQ3
DQM CS#
DQ0
DQ1 U12
DQ2
DQ3
DQM CS#
DQ0
DQ1 U13
DQ2
DQ3
DQ40
DQ41
DQ42
DQ43
DQM CS#
DQ0
DQ1 U20
DQ2
DQ3
DQM CS#
DQ0
DQ1 U29
DQ2
DQ3
DQM CS#
DQ0
DQ1 U30
DQ2
DQ3
DQM CS#
DQ0
DQ1 U31
DQ2
DQ3
DQ12
DQ13
DQ14
DQ15
DQM CS#
DQ0
DQ1 U3
DQ2
DQ3
DQM CS#
DQ0
DQ1 U4
DQ2
DQ3
DQ44
DQ45
DQ46
DQ47
DQM CS#
DQ0
DQ1 U21
DQ2
DQ3
DQM CS#
DQ0
DQ1 U22
DQ2
DQ3
CB0
CB1
CB2
CB3
RS3#
RS2#
RDQMB2
DQ16
DQ17
DQ18
DQ19
CB4
CB5
CB6
CB7
RDQMB6
DQM CS#
DQ0
DQ1 U5
DQ2
DQ3
DQM CS#
DQ0
DQ1 U6
DQ2
DQ3
DQM CS#
DQ0
DQ1 U14
DQ2
DQ3
DQM CS#
DQ0
DQ1 U15
DQ2
DQ3
DQ48
DQ49
DQ50
DQ51
DQM CS#
DQ0
DQ1 U23
DQ2
DQ3
DQM CS#
DQ0
DQ1 U24
DQ2
DQ3
DQM CS#
DQ0
DQ1 U32
DQ2
DQ3
DQM CS#
DQ0
DQ1 U33
DQ2
DQ3
DQ20
DQ21
DQ22
DQ23
RDQMB3
DQ24
DQ25
DQ26
DQ27
DQ52
DQ53
DQ54
DQ55
RDQMB7
DQM CS#
DQ0
DQ1 U7
DQ2
DQ3
DQM CS#
DQ0
DQ1 U8
DQ2
DQ3
DQM CS#
DQ0
DQ1 U16
DQ2
DQ3
DQM CS#
DQ0
DQ1 U17
DQ2
DQ3
DQ56
DQ57
DQ58
DQ59
DQM CS#
DQ0
DQ1 U25
DQ2
DQ3
DQM CS#
DQ0
DQ1 U26
DQ2
DQ3
DQM CS#
DQ0
DQ1 U34
DQ2
DQ3
DQM CS#
DQ0
DQ1 U35
DQ2
DQ3
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
RAS#
CAS#
CKE0
WE#
A0-A11
BA0
BA1
S0#-S3#
DQMB0 - DQMB7
10K
V
DD
REGE
PLL CLK
R
E
G
I
S
T
E
R
S
RRAS#: SDRAMs U0-U35
RCAS#: SDRAMs U0-U35
RCKE0: SDRAMs U0-U35
RWE#: SDRAMs U0-U35
RA0-RA11: SDRAMs U0-U35
RBA0: SDRAMs U0-U35
RBA1: SDRAMs U0-U35
RS0#-RS3#
RDQMB0 - RDQMB7
CK1-CK3
CK0
PLL
12pF
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
REGISTER x 3
12pF
SPD
SCL
WP
47K
SDA
A0
A1
A2
SA0 SA1 SA2
U0-U35 = MT48LC16M4A2F SDRAMs (256MB)
U0-U35 = MT48LC32M4A2F SDRAMs (512MB)
V
DD
V
SS
SDRAMs U0-U35
SDRAMs U0-U35
NOTE:
1. All resistor values are 10 ohms
unless otherwise specified.
2. Reference designators in this diagram
do not necessarily match the actual module.
32, 64 Meg x 72 Registered FBGA SDRAM DIMM
ZM32.p65 – Rev. 6/99
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
ADVANCE
32, 64 MEG x 72
REGISTERED FBGA SDRAM DIMM
PIN DESCRIPTIONS
PIN NUMBERS
27, 111, 115
42, 79, 125, 163
128
SYMBOL
RAS#, CAS#,
WE#
CK0-CK3
CKE0
TYPE
Input
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS# and WE# (along with
S0#-S3#) define the command being entered.
Clock: CK0 is distributed through an on-board PLL to all
devices. CK1-CK3 are terminated.
Clock Enable: CKE0 activates (HIGH) and deactivates
(LOW) the signal. Deactivating the clock provides POWER-
DOWN and SELF REFRESH operation (all banks idle) or
CLOCK SUSPEND operation (burst access in progress).
CKE0 is synchronous except after the device enters power-
down and self refresh modes, where CKE0 becomes
asynchronous until after exiting the same mode. The input
buffers, including CK0, are disabled during power-down and
self refresh modes, providing low standby power.
Chip Select: S0#-S3# enable (registered LOW) and disable
(registered HIGH) the command decoder. All commands
are masked when S0#-S3# are registered HIGH. S0#-S3#
are considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses.
Input data is masked when DQMB is sampled HIGH during
a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when DQMB is sampled HIGH
during a READ cycle.
Bank Address: BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE or PRECHARGE command is
being applied.
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE
command (column-address A0-A9 [256MB]/A0-A9, A11
[512MB], with A10 defining AUTO PRECHARGE) to select
one location out of the memory array in the respective bank.
A10 is sampled during a PRECHARGE command to
determine if both banks are to be precharged (A10 HIGH).
The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
Data I/O: Data bus.
30, 45, 114, 129
S0#-S3#
Input
28-29, 46-47,
112-113, 130-131
DQMB0-DQMB7
Input
39, 122
BA0, BA1
Input
33-38, 117-121, 123
A0-A11
Input
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89, 91-95,
97-101, 103-104,
139-142, 144, 149-151,
153-156, 158-161
21, 22, 52, 53, 105, 106,
136, 137
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110, 124,
133, 143, 157, 168
DQ0-DQ63
Input/
Output
CB0-CB7
V
DD
Input/
Output
Supply
Check Bits.
Power Supply: +3.3V
±0.3V.
32, 64 Meg x 72 Registered FBGA SDRAM DIMM
ZM32.p65 – Rev. 6/99
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
ADVANCE
32, 64 MEG x 72
REGISTERED FBGA SDRAM DIMM
PIN DESCRIPTIONS (continued)
PIN NUMBERS
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
81
82
SYMBOL
V
SS
TYPE
Supply
Ground.
DESCRIPTION
WP
SDA
Input
Write Protect: Serial presence-detect hardware write
protect.
Input/Output Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and data out of
the presence-detect portion of the module.
Input
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and from
the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Register Enable: REGE permits the DIMM to operate in
“buffered” mode (LOW) or “registered’ mode (HIGH).
Do Not Use: These pins are not connected on these
modules but are assigned pins on the compatible DRAM
versions.
83
SCL
165-167
147
31, 44, 48
SA0-SA2
REGE
DNU
Input
Input
–
32, 64 Meg x 72 Registered FBGA SDRAM DIMM
ZM32.p65 – Rev. 6/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
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