CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
AC PERFORMANCE
BW
-3dB Bandwidth
V
S
+ = +5V, V
S
- = -5V, R
F
= 392Ω for A
V
= 1, R
F
= 250Ω for A
V
= 2, R
L
= 150Ω, T
A
= +25°C
Unless Otherwise Specified.
CONDITIONS
MIN
TYP
MAX
UNIT
DESCRIPTION
A
V
= +1
A
V
= +2
1400
800
100
6000
8
1.7
19
50
MHz
MHz
MHz
V/µs
ns
nV/√Hz
pA/√Hz
pA/√Hz
%
°
BW1
SR
t
S
e
N
i
N
-
i
N
+
dG
dP
0.1dB Bandwidth
Slew Rate
0.1% Settling Time
Input Voltage Noise
IN- Input Current Noise
IN+ Input Current Noise
Differential Gain Error (Note 3)
Differential Phase Error (Note 3)
A
V
= +2
V
O
= -2.5V to +2.5V, A
V
= +2
V
OUT
= -2.5V to +2.5V, A
V
= -1
A
V
= +2
A
V
= +2
0.01
0.03
INPUT CHARACTERISTICS
C
IN
Input Capacitance
1.5
pF
ENABLE (5962-0625601QHC ONLY)
t
EN
t
DIS
NOTE:
3. Standard NTSC test, AC signal amplitude = 286mV, f = 3.58MHz.
Enable Time
Disable Time
170
1.25
ns
µs
2
FN6491.0
May 2, 2007
5962-0625601QHC, 5962-0625602QHC
Pin Descriptions
5962-0625601QHCIS
(10 LD FLAT PACK)
1, 5, 9, 10
2
5962-0625601QHCIS
(10 LD FLAT PACK)
1, 5, 8 , 9 ,10
2
PIN
NAME
NC
IN-
FUNCTION
Not connected
Inverting input
V
S
+
EQUIVALENT CIRCUIT
IN+
IN-
V
S
-
CIRCUIT 1
3
4
6
3
4
6
IN+
VS-
OUT
Non-inverting input
Negative supply
Output
(See circuit 1)
V
S
+
OUT
V
S
-
CIRCUIT 2
7
8
7
VS+
CE
Positive supply
Chip enable
V
S
+
CE
V
S
-
CIRCUIT 3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
FN6491.0
May 2, 2007
5962-0625601QHC, 5962-0625602QHC
Ceramic Metal Seal Flatpack Packages (Flatpack)
K10.A
MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)
e
-A-
b
PIN NO. 1
ID AREA
E1
0.004 M
H A-B S
D S
0.036 M
-B-
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
D
INCHES
SYMBOL
A
b
b1
MIN
0.045
0.015
0.015
0.004
0.004
-
0.240
-
0.125
0.030
0.008
0.250
0.026
0.005
-
10
MAX
0.115
0.022
0.019
0.009
0.006
0.290
0.260
0.280
-
-
0.015
0.370
0.045
-
0.0015
MILLIMETERS
MIN
1.14
0.38
0.38
0.10
0.10
-
6.10
-
3.18
0.76
1.27 BSC
0.20
6.35
0.66
0.13
-
10
0.38
9.40
1.14
-
0.04
MAX
2.92
0.56
0.48
0.23
0.15
7.37
6.60
7.11
-
-
NOTES
-
-
-
-
-
3
-
3
-
7
-
2
-
8
6
-
-
Rev. 0 3/07
S1
H A-B S
D S
c
c1
D
E
E1
E2
E3
e
k
L
Q
S1
M
N
Q
A
-C-
E
C
-D-
-H-
L
E3
E2
E3
LEAD FINISH
L
SEATING AND
BASE PLANE
0.050 BSC
c1
BASE
METAL
b1
M
M
(b)
SECTION A-A
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
PCB设计
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