IDT74LVCH16702A
3.3V CMOS 18-BIT READ/WRITE BUFFER, 5 VOLT TOLERANT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
READ/WRITE BUFFER
WITH 5 VOLT TOLERANT I/O
FEATURES:
–
–
–
–
–
–
–
–
–
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
Extended commercial range of -40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4µ W typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
IDT74LVCH16702A
DESCRIPTION:
The LVCH16702A 18-bit read/write buffer is built using advanced dual
metal CMOS technology. The device is designed as an 18-bit read/write
buffer with a four deep FIFO and a read-back latch. It can be used as a read/
write buffer between a CPU and a memory or to interface a high-speed bus
and a slow peripheral. The A-to-B (write) path has a four deep FIFO for
pipelined operations. The FIFO can be reset and a FIFO full condition is
indicated by the full flag (FF). The B-to-A (read) path has a latch.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH16702A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16702A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
Drive Features for LVCH16702A:
– High Output Drivers: ±24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
A
1:18
18
28
CE
55
CLK
RESET
29
27
OEBA
Q
W CE
RCE
FF
30
2
56
FIFO
(4 deep)
CE
REGISTER
D
OEAB
1
18
B
1:18
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1998
DSC-4234/-
IDT74LVCH16702A
3.3V CMOS 18-BIT READ/WRITE BUFFER, 5 VOLT TOLERANT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
°C
mA
mA
mA
LVC Link
Max.
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
OEAB
W CE
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
SO56-1
14 SO56-2
15 SO56-3
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RCE
CLK
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
FF
RESET
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
LVC Link
NOTE:
1. As applicable to the device type.
SSOP/ TSSOP/ TVSOP
TOP VIEW
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVCH16702A
3.3V CMOS 18-BIT READ/WRITE BUFFER, 5 VOLT TOLERANT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names
A
1-18
B
1-18
CLK
WCE
RCE
FF
RESET
OEAB
OEBA
CE
I/O
I/O
I/O
I
I
I
O
I
I
I
I
18 bit I/O port.
18 bit I/O port.
Clock Input.
Enable pin for FIFO input clock. When
WCE
is low data clocks into the FIFO on the rising edge of CLK.
Enable pin for FIFO output clock. When
RCE
is low data clocks out of the FIFO on the rising edge of CLK.
Write path FIFO full flag. Goes low when FIFO is full. When FIFO is full all further writes to the FIFO are inhibited. When FIFO
is empty all reads from the FIFO are inhibited.
Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the "empty" condition and FIFO
output is forced high (all ones). The FIFO full flag (FF) will be high immediately after reset.
Output Enable pin for B port.
Output Enable pin for A port.
Clock Enable pin for B to A register.
Description
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs, outputs, or I/Os.
FUNCTIONAL TABLE
INPUTS
OEBA
L
L
H
H
L
L
H
OEAB
H
H
H
L
L
L
H
CE
L
H
L
X
L
H
H
CLK
↑
↑
↑
↑
↑
↑
↑
(1)
OUTPUTS
A
B to A
Q
0
(A)
Q
0
(A)Bus Hold
A to B signal is delayed by 4 clocks
Q
0
(A) - 5 clocks
Q
0
(B)
Q
0
(A)Bus Hold
Q
0
(A) - 5 clocks
Q
0
(B) Bus hold
See timing diagram
Case not recommended
Case not recommended
B
B Bus Activity
B Bus Activity
Notes
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= Low-to-High Transition
Q
0
= Level of Q before the indicated steady-state input conditions were established.
FUNCTIONAL DESCRIPTION
This device is useful as a read/write buffer for modular high end designs.
It provides multi-level buffering in the write path and single deep buffering
in the read path, and is suited to write back cache implementation. The read
path provides a register for full synchronous operation.
The four deep FIFO uses one clock with two clock enable pins,
WCE
and
RCE
to clock data in and out. The FIFO has an external full flag which goes
LOW when the FIFO is full. Internal read and write pointers keep track of
the words stored in the FIFO. A write attempt to a full FIFO is ignored. An
attempt to read from an empty FIFO will have no effect and the last read data
remains at the output of the FIFO. The FIFO may be reset by the
synchronous
RESET
input. This resets the read and write pointers to the
original “empty” condition and also sets all B outputs = 1. Simultaneous read
and write attempts (clock data into FIFO as well as clock data out of FIFO)
are possible except on FIFO empty and full boundaries. When the FIFO
is empty, and a simultaneous read and write is attempted, the read is ignored
while the write is executed. If the same is attempted when the FIFO is full,
the write is ignored while the read is executed. Normal operation of the four
deep FIFO in the write path is independent of the read path operation.
3
IDT74LVCH16702A
3.3V CMOS 18-BIT READ/WRITE BUFFER, 5 VOLT TOLERANT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
TIMING DIAGRAM
WRITE CYCLES
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 1
READ CYCLES
Cycle 2
Cycle 3
Cycle 4
CLK
RESET
WCE
OEAB
A [1:18]
WORD 1
WORD 2
WORD 3
WORD 4
FF
B [1:18]
WORD 1
WORD 2
WORD 3
WORD 4
RCE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40
O
C to +85
O
C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
3.6
≤
V
IN
≤
5.5V
(2)
Quiescent Power Supply
Current Variation
One input at V
CC
- 0.6V
other inputs at V
CC
or GND
—
—
—
—
—
—
—
– 0.7
100
—
—
—
±50
– 1.2
—
10
10
500
µA
LVC Link
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
Unit
V
V
µA
µA
µA
V
mV
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
4
IDT74LVCH16702A
3.3V CMOS 18-BIT READ/WRITE BUFFER, 5 VOLT TOLERANT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
LVC Link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
—
—
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
LVC Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V
±
0.3V, TA = 25°C
Symbol
C
PD
C
PD
C
PD
C
PD
Parameter
Power Dissipation WCE Mode
OEAB
= 0
Power Dissipation in RCE mode
OEBA
= 0
Registered channel (B to A)
Power Dissipation
OEBA
= 0;
CE
= 0
Registered channel
Power Dissipation
OEBA
= 0:
CE
= 1
Test Conditions
Typical
Unit
pF
pF
C
L
= 0pF, f = 10Mhz
pF
pF
5
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