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HY5Y2B6DLF-HE: 产品描述4Banks x 2M x 16bits Synchronous DRAM; 产品类别存储存储; 文件大小327KB，共26页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HY5Y2B6DLF-HE概述

4Banks x 2M x 16bits Synchronous DRAM

HY5Y2B6DLF-HE规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	SK Hynix(海力士)
零件包装代码	BGA
包装说明	TFBGA, BGA54,9X9,32
针数	54
Reach Compliance Code	unknow
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	5.4 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz
I/O 类型	COMMON
交错的突发长度	1,2,4,8
JESD-30 代码	R-PBGA-B54
JESD-609代码	e0
长度	8 mm
内存密度	134217728 bi
内存集成电路类型	SYNCHRONOUS DRAM
内存宽度	16
功能数量	1
端口数量	1
端子数量	54
字数	8388608 words
字数代码	8000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-25 °C
组织	8MX16
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TFBGA
封装等效代码	BGA54,9X9,32
封装形状	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	3 V
认证状态	Not Qualified
刷新周期	4096
座面最大高度	1.2 mm
自我刷新	YES
连续突发长度	1,2,4,8,FP
最大待机电流	0.00035 A
最大压摆率	0.22 mA
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	2.7 V
标称供电电压 (Vsup)	3 V
表面贴装	YES
技术	CMOS
温度等级	OTHER
端子面层	Tin/Lead (Sn/Pb)
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	8 mm

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HY5Y2B6DLF(P) Series

4Banks x 2M x 16bits Synchronous DRAM

Document Title

4Bank x 2M x 16bits Synchronous DRAM

Revision History

Revision No.

0.1

0.2

0.3

History

Initial Draft

Changed Current Spec. of IDD1, 4 and 5

Deleted Preliminary

Draft Date

Dec. 2003

Apr. 2004

May. 2004

Remark

Preliminary

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.3 / May. 2004

HY5Y2B6DLF(P) Series

4Banks x 2M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix Mobile SDR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular

phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.

The Hynix HY5Y2B6DLF(P) is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It is organized

as 4banks of 2,097,152x16.

The Mobile SDR provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of

1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Mobile SDR also provides for

special programmable options including Partial Array Self Refresh of a quarter bank, a half bank, 1bank, 2banks, or all

banks.

The Hynix HY5Y2B6DLF(P) has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh)

to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automati-

cally adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write cycles in

progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or

Write command on any cycle(This pipelined design is not restricted by a 2N rule).

Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power re-

duction by removing power to the memory array within each SDR. By using this feature, the system can cut off alomost

all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility.

FEATURES

●

Standard SDR Protocol

Internal 4bank operation

Voltage : VDD = 3.0V, VDDQ = 3.0V

LVCMOS compatible I/O Interface

Low Voltage interface to reduce I/O power

Low Power Features

- PASR(Partial Array Self Refresh)

- AUTO TCSR (Temperature Compensated Self Refresh)

- DS (Drive Strength)

- Deep Power Down Mode

Programmable CAS latency of 1, 2 or 3

Package : 54 Ball FBGA (Lead, Lead Free)

- HY5Y2B6DLF Seriese : Lead

- HY5Y2B6DLFP Seriese : Lead Free

●

ORDERING INFORMATION

Part Number

HY5Y2B6DLF(P)-HE

Clock Frequency

133MHz

CAS

Latency

Organization

4banks x 2Mb x 16

Interface

LVCMOS

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.3 / May. 2004

HY5Y2B6DLF-HE相似产品对比

	HY5Y2B6DLF-HE	HY5Y2B6DLFP-HE
描述	4Banks x 2M x 16bits Synchronous DRAM	4Banks x 2M x 16bits Synchronous DRAM
是否Rohs认证	不符合	符合
厂商名称	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	BGA	BGA
包装说明	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32
针数	54	54
Reach Compliance Code	unknow	unknow
ECCN代码	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	5.4 ns	5.4 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz	133 MHz
I/O 类型	COMMON	COMMON
交错的突发长度	1,2,4,8	1,2,4,8
JESD-30 代码	R-PBGA-B54	R-PBGA-B54
JESD-609代码	e0	e1
长度	8 mm	8 mm
内存密度	134217728 bi	134217728 bi
内存集成电路类型	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	16	16
功能数量	1	1
端口数量	1	1
端子数量	54	54
字数	8388608 words	8388608 words
字数代码	8000000	8000000
工作模式	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	85 °C
最低工作温度	-25 °C	-25 °C
组织	8MX16	8MX16
输出特性	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFBGA	TFBGA
封装等效代码	BGA54,9X9,32	BGA54,9X9,32
封装形状	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
电源	3 V	3 V
认证状态	Not Qualified	Not Qualified
刷新周期	4096	4096
座面最大高度	1.2 mm	1.2 mm
自我刷新	YES	YES
连续突发长度	1,2,4,8,FP	1,2,4,8,FP
最大待机电流	0.00035 A	0.00035 A
最大压摆率	0.22 mA	0.22 mA
最大供电电压 (Vsup)	3.6 V	3.6 V
最小供电电压 (Vsup)	2.7 V	2.7 V
标称供电电压 (Vsup)	3 V	3 V
表面贴装	YES	YES
技术	CMOS	CMOS
温度等级	OTHER	OTHER
端子面层	Tin/Lead (Sn/Pb)	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL	BALL
端子节距	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM
宽度	8 mm	8 mm

HY5Y2B6DLF-HE

HY5Y2B6DLF-HE概述

HY5Y2B6DLF-HE规格参数

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