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HY5S5B2BLF-SE: 产品描述256M (8Mx32bit) Mobile SDRAM; 产品类别存储存储; 文件大小672KB，共54页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HY5S5B2BLF-SE概述

256M (8Mx32bit) Mobile SDRAM

HY5S5B2BLF-SE规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	SK Hynix(海力士)
零件包装代码	BGA
包装说明	VFBGA, BGA90,9X15,32
针数	90
Reach Compliance Code	unknow
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	7 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	105 MHz
I/O 类型	COMMON
交错的突发长度	1,2,4,8
JESD-30 代码	R-PBGA-B90
长度	13 mm
内存密度	268435456 bi
内存集成电路类型	SYNCHRONOUS DRAM
内存宽度	32
功能数量	1
端口数量	1
端子数量	90
字数	8388608 words
字数代码	8000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-25 °C
组织	8MX32
封装主体材料	PLASTIC/EPOXY
封装代码	VFBGA
封装等效代码	BGA90,9X15,32
封装形状	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	1.8 V
认证状态	Not Qualified
刷新周期	4096
座面最大高度	1 mm
自我刷新	YES
连续突发长度	1,2,4,8,FP
最大待机电流	0.0003 A
最大压摆率	0.1 mA
最大供电电压 (Vsup)	1.95 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	OTHER
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	8 mm

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256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O

Specification of

256M (8Mx32bit) Mobile SDRAM

Memory Cell Array

- Organized as 4banks of 2,097,152 x32

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.0 / Apr. 2006

256Mbit (8Mx32bit) Mobile SDR Memory

HY5S5B2BLF(P) Series

DESCRIPTION

The Hynix HY5S5B2BLF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular

phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.

The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the

main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of

2,097,152 x32.

Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch

each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the

input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/

Output bus. All the commands are latched in synchronization with the rising edge of CLK.

The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8

locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is ini-

tiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed

operation. This architecture is compartible with the

rule of prefetch architectures, but it also allows the column

address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while

accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-

access operation.

Read and write accesses to the Hynix Mobile SDRAMs are burst oriented;

accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.

The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be

accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and

the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a

burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any

cycle(This pipelined design is not restricted by a

rule).

The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array,

half array, quarter array, 1/8 array, Temperature Compensated Self Refresh of 40 or 85 degrees

The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to

reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically

adjust refresh rate according to temperature without external EMRS command.

Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power

reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut

off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout

flexibility.

All inputs are LV-CMOS compatible. Devices will have a V

and V

DDQ

supply of 1.8V (nominal).

Rev 1.0 / Apr. 2006

HY5S5B2BLF-SE相似产品对比

	HY5S5B2BLF-SE	HY5S5B2BLF-HE	HY5S5B2BLF-6E	HY5S5B2BLFP-6E	HY5S5B2BLFP-HE
描述	256M (8Mx32bit) Mobile SDRAM	256M (8Mx32bit) Mobile SDRAM	256M (8Mx32bit) Mobile SDRAM	256M (8Mx32bit) Mobile SDRAM	256M (8Mx32bit) Mobile SDRAM
是否Rohs认证	不符合	不符合	不符合	符合	符合
厂商名称	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	BGA	BGA	BGA	BGA	BGA
包装说明	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32
针数	90	90	90	90	90
Reach Compliance Code	unknow	unknow	unknown	unknow	unknow
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	7 ns	6.5 ns	5.4 ns	5.4 ns	6.5 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	105 MHz	133 MHz	166 MHz	166 MHz	133 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON
交错的突发长度	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 代码	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90
长度	13 mm	13 mm	13 mm	13 mm	13 mm
内存密度	268435456 bi	268435456 bi	268435456 bit	268435456 bi	268435456 bi
内存集成电路类型	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	32	32	32	32	32
功能数量	1	1	1	1	1
端口数量	1	1	1	1	1
端子数量	90	90	90	90	90
字数	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words
字数代码	8000000	8000000	8000000	8000000	8000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-25 °C	-25 °C	-25 °C	-25 °C	-25 °C
组织	8MX32	8MX32	8MX32	8MX32	8MX32
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	VFBGA	VFBGA	VFBGA	VFBGA	VFBGA
封装等效代码	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	260	260
电源	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	4096	4096	4096	4096
座面最大高度	1 mm	1 mm	1 mm	1 mm	1 mm
自我刷新	YES	YES	YES	YES	YES
连续突发长度	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
最大待机电流	0.0003 A	0.0003 A	0.0003 A	0.0003 A	0.0003 A
最大压摆率	0.1 mA	0.1 mA	0.1 mA	0.1 mA	0.1 mA
最大供电电压 (Vsup)	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	OTHER	OTHER	OTHER	OTHER	OTHER
端子形式	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	20	20
宽度	8 mm	8 mm	8 mm	8 mm	8 mm

HY5S5B2BLF-SE

HY5S5B2BLF-SE概述

HY5S5B2BLF-SE规格参数

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