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SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
D
D
D
D
D
D
Bus Transceivers/Registers
Independent Registers and Enables for A
and B Buses
Multiplexed Real-Time and Stored Data
Choice of True or Inverting Data Paths
Choice of 3-State or Open-Collector
Outputs to A Bus
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
DEVICE
A OUTPUT
3 State
B OUTPUT
3 State
LOGIC
Inverting
SN54ALS’, SN54AS’ . . . JT PACKAGE
SN74ALS’, SN74AS’ . . . DW OR NT PACKAGE
(TOP VIEW)
SN74ALS651A,
’AS651
SN54ALS652,
SN74ALS652A,
’AS652
’ALS653
SN74ALS654
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
3 State
Open Collector
Open Collector
3 State
3 State
3 State
True
Inverting
True
SN54ALS’, SN54AS’ . . . FK PACKAGE
(TOP VIEW)
description
A1
A2
A3
NC
A4
A5
A6
5
OEAB
SAB
CLKAB
NC
V
CC
CLKBA
SAB
4
3 2 1 28 27 26
25
These devices consist of bus-transceiver circuits,
6
24
B1
D-type flip-flops, and control circuitry arranged for
7
23
B2
multiplexed transmission of data directly from the
8
22
NC
data bus or from the internal storage registers.
9
21
B3
Output-enable (OEAB and OEBA) inputs are
10
20
B4
provided to control the transceiver functions.
11
19
B5
Select-control (SAB and SBA) inputs are provided
12 13 14 15 16 17 18
to select real-time or stored data transfer. The
circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time
NC – No internal connection
data. A low input level selects real-time data, and
a high input level selects stored data. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the octal bus
transceivers and registers.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
A7
A8
GND
NC
B8
B7
B6
OEBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
description (continued)
The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the
recommended maximum I
OL
for the -1 versions is increased to 48 mA. There are no -1 versions of the
SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654.
The SN54ALS’ and SN54AS’ families are characterized for operation over the full military temperature range
of – 55°C to 125°C. The SN74ALS’ and SN74AS’ families are characterized for operation from 0°C to 70°C.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
BUS B
3
21
OEAB OEBA
L
L
1
23
2
CLKAB CLKBA SAB
X
X
X
22
SBA
L
3
21
OEAB OEBA
H
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
BUS B
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
1
CLKAB
H or L
23
CLKBA
H or L
2
SAB
H
BUS B
22
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
BUS A
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
BUS A
3
OEAB
X
L
L
21
OEBA
H
X
H
1
↑
X
↑
23
X
↑
↑
2
X
X
X
22
SBA
X
X
X
3
OEAB
H
CLKAB CLKBA SAB
OEBA
L
STORAGE FROM
A, B, OR A AND B
Pin numbers are for the DW, JT, and NT packages.
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
BUS A
21
BUS A
3
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
FUNCTION TABLES
SN54ALS653, SN54AS651,
SN74ALS651A, SN74ALS653, SN74AS651
DATA I/O†
CLKBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
SAB
X
X
X
X‡
X
X
X
X
L
H
H
SBA
X
X
X
X
X
X‡
L
H
X
X
H
A1– A8
Input
Input
Input
Input
Unspecified‡
Output
Output
Output
Input
Input
Output
B1– B8
Input
Input
Unspecified‡
Output
Input
Input
Input
Input
Output
Output
Output
INPUTS
OEAB
L
L
X
H
L
L
L
L
H
H
H
OEBA
H
H
H
H
X
L
L
L
H
H
L
CLKAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
OPERATION OR FUNCTION
Isolation
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
Stored A data to B bus and
stored B data to A bus
† The data output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
‡ Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
SN54ALS652, SN54AS652,
SN74ALS652A, SN74ALS654, SN74AS652
DATA I/O†
CLKBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
SAB
X
X
X
X‡
X
X
X
X
L
H
H
SBA
X
X
X
X
X
X‡
L
H
X
X
H
A1– A8
Input
Input
Input
Input
Unspecified‡
Output
Output
Output
Input
Input
Output
B1– B8
Input
Input
Unspecified‡
Output
Input
Input
Input
Input
Output
Output
Output
INPUTS
OEAB
L
L
X
H
L
L
L
L
H
H
H
OEBA
H
H
H
H
X
L
L
L
H
H
L
CLKAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
OPERATION OR FUNCTION
Isolation
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
Stored A data to B bus and
stored B data to A bus
† The data output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
‡ Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
4
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•
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