HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
1Gb DDR2 SDRAM
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.7 / Oct. 2007
1
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
Revision Details
Rev.
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Initial data sheet released
Typo corrected
Leakage current spec added and IDD value updated
Removed improper note in ODT DC spec
Added tDS/tDH(single ended strobe) parameter
Inserted Pin Description & Adjusted IDD spec values
Corrected Typo
History
Draft Date
Mar. 2006
May. 2006
May. 2006
July. 2006
Aug. 2006
Mar. 2007
Oct. 2007
Rev. 0.7 / Oct. 2007
2
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Features
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
3.1.1 Recommended DC Operating Conditions(SSTL_1.8)
3.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 0.7 / Oct. 2007
3
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
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VDD=1.8V +/- 0.1V
VDDQ=1.8 +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write(centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 3, 4 and 5 supported
Programmable additive latency 0, 1, 2, 3 and 4supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal eight bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 68ball FBGA(x4/x8) , 92ball FBGA(x16)
Full strength driver option controlled by EMRS
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe supported (x8 only)
Self-Refresh High Temperature Entry
Ordering Information
Part No.
HY5PS1G431A(L)FP-XX*
HY5PS1G831A(L)FP-XX*
HY5PS1G1631A(L)FP-XX*
Note:
Configuration Package
256Mx4
128Mx8
64Mx16
92 Ball
68 Ball
Operating Frequency
Grade
E3
C4
Y5
tCK(ns)
5
3.75
3
CL
3
4
5
tRCD
3
4
5
tRP
3
4
5
Unit
Clk
Clk
Clk
XX* is the speed bin, refer to the Operation Frequency table for complete part number.
Hynix lead-free products are compliant to RoHS.
Rev. 0.7 / Oct. 2007
4
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
1.2 Pin Configuration & Address Table
256Mx4 DDR2 Pin Configuration
(Top view: see balls through package)
1
NC
2
NC
3
A
B
C
D
7
8
NC
9
NC
VDD
NC
VDDQ
NC
VDDL
NC
VSSQ
DQ1
VSSQ
VREF
CKE
VSS
DM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VDDQ
NC
VDDQ
NC
VDD
ODT
BA2
BA0
A10
VDD
VSS
A3
A7
VSS
VDD
A12
NC
NC
W
NC
NC
ROW AND COLUMN ADDRESS TABLE
ITEMS
# of Bank
Bank Address
Auto Precharge Flag
Row Address
Column Address
Page size
Rev. 0.7 / Oct. 2007
5
256Mx4
8
BA0,BA1,BA2
A10/AP
A0 - A13
A0-A9, A11
1 KB
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