HY5FS123235AFCP
512M (16Mx32) GDDR4 SDRAM
HY5FS123235AFCP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2/June. 2008
1
HY5FS123235AFCP
Revision History
Revision No.
0.0
0.1
1.0
Defined target spec.
Inserted AC timing and IDD value
1. Changed a marking method of tWL on page 57
2. Changed tWR from 24 to 20 on page 58.
3. Changed DLL on/off frequency to 2.5ns on page 57, page 59
(note 9) and page 60 (note 40).
5. Optimized IDD value and AC timing table on page 56, 57.
1. Revised typoes
1. Revised typoes on page 67
History
Draft Date
Aug. 2006
Apr. 2007
May. 2007
Remark
Preliminary
Preliminary
1.1
1.2
May. 2007
Jun. 2008
Rev. 1.2 /June. 2008
2
HY5FS123235AFCP
TABLE OF CONTENTS
FEATURES........................................................................................................................................................5
FEATURES..............................................................................................................................................5
FUNCTIONAL DESCRIPTION....................................................................................................................5
INITIALIZATION................................................................................................................................................6
REGISTER DEFINITION......................................................................................................................................8
MODE REGISTER.....................................................................................................................................8
EXTENDED MODE REGISTER..................................................................................................................12
EXTENDED MODE REGISTER2................................................................................................................15
EXTENDED MODE REGISTER3................................................................................................................16
COMMAND & ADDRESS.....................................................................................................................................17
Addressing.............................................................................................................................................17
Commands.............................................................................................................................................18
OPERATION.....................................................................................................................................................19
Deselect.................................................................................................................................................19
No Operation (NOP)................................................................................................................................19
MODE REGISTER SET..............................................................................................................................19
Activation...............................................................................................................................................19
Data Terminator Disable..........................................................................................................................20
Bank Restrictions....................................................................................................................................20
READ.....................................................................................................................................................21
READ and DLL Off Mode.........................................................................................................................24
WRITE...................................................................................................................................................25
PRECHARGE...........................................................................................................................................28
AUTO PRECHARGE.................................................................................................................................28
AUTO REFRESH.....................................................................................................................................28
SELF REFRESH.......................................................................................................................................29
Power Down..........................................................................................................................................31
READ and WRITE DBI............................................................................................................................36
CLOCKING, DATA CAPTURE....................................................................................................................41
Data Capture........................................................................................................................................41
Data Training.........................................................................................................................................42
Read Data Training Sequence.........................................................................................................42
Write Data Training Sequence........................................................................................................44
Changing Clock Frequency.....................................................................................................................46
DRIVER & TERMINATION..................................................................................................................................49
Programmable Impedance Output Buffer and Active Terminator...............................................................49
Impedance Control................................................................................................................................49
Data Terminator Disable........................................................................................................................50
Rev. 1.2 /June. 2008
3
HY5FS123235AFCP
LPTERM...............................................................................................................................................51
OPERATING CONDITIONS..................................................................................................................................52
Absolute Maximum Ratings......................................................................................................................52
AC & DC Characteristics...........................................................................................................................53
1.5V I/O Driver Values.............................................................................................................................61
1.8V I/O Driver Values............................................................................................................................62
2.0V I/O Driver Values............................................................................................................................63
POD I/O SYSTEM..............................................................................................................................................64
PACKAGE SPECIFICATION.................................................................................................................................67
Ball-out..................................................................................................................................................67
Signals...................................................................................................................................................68
Mirror Function.......................................................................................................................................70
Package Dimensions...............................................................................................................................71
Vendor ID..............................................................................................................................................72
Rev. 1.2 /June. 2008
4
HY5FS123235AFCP
FEATURES
• Double-data rate architecture;
two data transfers per clock cycle
• Single ended READ strobe (RDQS) per byte
• Single ended WRITE strobe (WDQS) per byte
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge;
data and data mask referenced to both edges
of RDQS/WDQS
• Eight internal banks for concurrent operation
• Data mask (DM) for masking WRITE data
• Burst Length: 8 only
• Multiplexed addressing
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• On die termination (ODT)
• Calibrated output drive
• Programmable offset for both driver and termination
• POD_18 compatible inputs/outputs
• VDD and VDDQ: 1.8V +/- 5%, 2.0V +/- 5%
• CAS Latency : 7~22
A single read or write access for the
Hynix HY5FS123235AFCP effectively consists of an 8N
data transfer every four clock-cycles at the inernal
DRAM core and eight corresponding n-bit wide, one-half-
clock-cycle data transfers at the I/O pins.
Uni-directional data strobes are transmitted
externally, along with data, for use in data capture
at the receiver. RDQS is a strobe transmitted by the
GDDR4 SDRAM during READs. WDQS is the data strobe
sent by the memory controller during WRITEs.
RDQS is edge aligned with data for READs and WDQS is
center aligned with data for WRITEs.
The GDDR4 SDRAM operates from a differential clock
(CK and CK# the crossing of the CK going high and
CK# going low will be referred to as the positive edge
of CK). Commands (address and control signals)
are registered at the positive edge of CK.
Address is received on two consecutive rising edges of
CK. Input data is registered at both edges of WDQS,
and output data is referenced to both edges of RDQS,
as well as to both edges of CK.
FUNCTIONAL DESCRIPTION
The Hynix HY5FS123235AFCP is a high speed CMOS,
dynamic random access memory internally configured as
a eight bank DRAM.
These devices contain the following number of bits:
512M has 536,870,912 bits and eight banks
Read and write accesses to the GDDR4 SDRAM are
burst oriented; accesses start at a selected location
and continue for a total of eight locations. Accesses begi
n with the registration of an ACTIVE command, which is
The Hynix HY5FS123235AFCP uses a double data rate
then followed by a READ or WRITE command.
architecture to achieve high speed operation.
The address bits registered coincident with the ACTIVE
The double data rate architecture is essentially an 8N
command are used to select the bank and the row to be
prefetch architecture with an interface designed to transfer accessed. The address bits registered coincident with the
two data words per clock cycle at the I/O pins.
READ or WRITE command are used to select the bank
and the starting column locaion for the burst access.
ORDERING INFORMATION
Part No.
HY5FS123235AFCP-06
HY5FS123235AFCP- 07
HY5FS123235AFCP- 08
HY5FS123235AFCP- 09
Power Supply
VDD/VDDQ = 2.0V
VDD/VDDQ = 1.8V
Clock Frequency
1.6GHz
1.4GHz
1.2GHz
1.1GHz
Max Data Rate
3.2Gbps/pin
2.8Gbps/pin
2.4Gbps/pin
2.2Gbps/pin
POD_18
Interface
Note:
Above Hynix P/N’s and their homogeneous Subcomponents are RoHS(& Lead free) Compliant.
Rev. 1.2 /June. 2008
5
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