SRAM
Austin Semiconductor, Inc.
256K x 1 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-88725
• SMD 5962-88544
• MIL-STD-883
MT5C2561
PIN ASSIGNMENT
(Top View)
24-Pin DIP (C)
(300 MIL)
A6
A7
A8
A9
A10
A11
A14
A15
A0
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
A5
A4
A3
A2
A1
A17
A16
A13
A12
D
CE\
FEATURES
High Speed: 35, 45, 55, and 70
Battery Backup: 2V data retention
Low power standby
High-performance, low-power, CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
•
•
•
•
28-Pin LCC (EC)
• Timing
35ns access
45ns access
55ns access
70ns access
• Package(s)
Ceramic DIP (300 mil)
Ceramic LCC
A8
A7
A6
Vcc
A17
OPTIONS
MARKING
-35
-45
-55*
-70*
NC 4
A9 5
A10 6
A11 7
A14 8
A15 9
A0 10
Q 11
NC 12
3 2 1 28 27
26
25
24
23
22
21
20
19
18
13 14 15 16 17
A12
D
CE\
Vss
WE\
NC
A4
A3
A2
A1
A17
A16
A13
NC
C
EC
No. 106
No. 204
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS and are fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Austin Semiconductor offers chip enable (CE\) on all organiza-
tions. This enhancement can place the outputs in High-Z for
additional flexibility in system design. The x1 configuration
features separate data input and output.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ goes LOW. The
device offers a reduced power standby mode when disabled.
This allows system designs to achieve low standby power re-
quirements.
These devices operate from a single +5V power sup-
ply and all inputs and outputs are fully TTL compatible.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C2561
Rev. 2.6 06/05
1
SRAM
Austin Semiconductor, Inc.
MT5C2561
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
A13
A14
A15
A16
A17
A0
A1
A2
A3
A4
D
ROW DECODER
I/O CONTROL
Q
262,144-BIT
MEMORY ARRAY
CE\
WE\
POWER
DOWN
COLUMN DECODER
A5
A6
A7
A8
A9
A10
A11 A12
TRUTH TABLE
MODE
CE\
STANDBY H
READ
L
WRITE
L
WE\
X
H
L
DQ
HIGH-Z
Q
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
MT5C2561
Rev. 2.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss..................................-0.5V to +7V
Voltage on Vcc Supply Relative to Vss.............................-0.5V to +7V
Voltage Applied to Q.........................................................-0.5V to +6V
Storage Temperature......................................................-65
o
C to +150
o
C
Power Dissipation..............................................................................1W
Short Circuit Output Current.........................................................50mA
Lead Temperature (soldering 10 seconds)....................................+260
o
C
Junction Temperature..................................................................+175
o
C
MT5C2561
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
0V<V
IN
<V
CC
Output(s) disabled
0V<V
OUT
<V
CC
I
OH
= -4.0mA
I
OL
= 8.0mA
CONDITIONS
SYM
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
MIN
2.2
-0.5
-10
-10
2.4
0.4
MAX
V
CC
+0.5
0.8
10
10
UNITS
V
V
µA
µA
V
V
1
1
NOTES
1
1, 2
PARAMETER
Power Supply
Current: Operating
CONDITIONS
SYM
I
CCSP
MAX
-35
-45
120
120
UNITS NOTES
mA
3
CE\ < V
IL
; V
CC
= MAX
f = MAX = 1/t
RC
(MIN)
Output Open
I
CCLP
CE\ > V
IH
; All Other Inputs
< V
IL
or > V
IH
, V
CC
= MAX
f = 0 Hz
CE\ > V
CC
-0.2V; V
CC
= MAX
V
IL
< V
SS
+0.2V
V
IH
> V
CC
-0.2V; f = 0 Hz
"L" Version Only
I
SBT1
100
100
mA
3
Power Supply
Current: Standby
25
25
mA
I
SBCSP
I
SBCLP
20
3
20
3
mA
mA
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
MT5C2561
Rev. 2.6 06/05
CONDITIONS
T
A
= 25 C, f = 1MHz
Vcc = 5V
o
SYM
C
I
C
O
3
MAX
10
12
UNITS
pF
pF
NOTES
4
4
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SRAM
Austin Semiconductor, Inc.
MT5C2561
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
-35
SYMBOL
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
MIN
35
35
35
3
3
20
0
35
35
30
30
0
5
30
20
0
0
0
45
40
40
0
5
40
20
0
0
0
0
45
3
3
20
MAX
MIN
45
45
45
-45
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
7
6, 7
4
4
15
20
7
6, 7
MT5C2561
Rev. 2.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
MT5C2561
167Ω
Q
30pF
V
TH
= 1.73V Q
167Ω
5pF
V
TH
= 1.73V
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE
, t
LZWE
, t
LZOE
, t
HZCE
, t
HZOE
and t
HZWE
are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
4.
5.
6.
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition, t
HZCE
is
less than t
LZCE
, and t
HZWE
is less than t
LZWE
and t
HZOE
is
less than t
LZOE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. t
RC
= Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
CONDITIONS
SYM
V
DR
CE\ > (V
CC
- 0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
I
CCDR
900
µA
MIN
2
MAX
---
UNITS
V
NOTES
t
CDR
t
R
0
t
RC
---
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
V
DR
> 2V
4.5V
t
R
V
DR
CE\
V
IH
V
IL
MT5C2561
Rev. 2.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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