HM514260D Series
HM51S4260D Series
262,144-word
×
16-bit Dynamic RAM
ADE-203-510A (Z)
Rev. 1.0
Dec. 2, 1996
Description
The Hitachi HM51(S)4260D is CMOS dynamic RAM organized as 262,144-word
×
16-bit. HM51(S)4260D
has realized higher density, higher performance and various functions by employing 0.8
µm
CMOS process
technology and some new CMOS circuit design technologies. The HM51(S)4260D offers Fast Page Mode as
a high speed access mode. Multiplexed address input permits the HM51(S)4260D to be packaged in standard
400-mil 40-pin plastic SOJ, and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables
HM51S4260D self refresh operation.
Features
•
Single 5 V
•
Access time: 60 ns/70 ns/80 ns (max)
•
Power dissipation
Active mode:
825 mW/770 mW/688 mW (max)
Standby mode: 11 mW (max)
1.1 mW (max) (L-version)
•
Fast page mode capability
512 refresh cycles:
8 ms
128 ms (L-version)
•
2
CAS
byte control
•
2 variations of refresh
RAS-only
refresh
CAS-before-RAS
refresh
•
Battery back up operation (L-version)
•
Self refresh operation (HM51S4260D/DL)
HM514260D, HM51S4260D Series
Ordering Information
Type No.
HM514260DJ-6
HM514260DJ-7
HM514260DJ-8
HM514260DLJ-6
HM514260DLJ-7
HM514260DLJ-8
HM51S4260DJ-6
HM51S4260DJ-7
HM51S4260DJ-8
HM51S4260DLJ-6
HM51S4260DLJ-7
HM51S4260DLJ-8
HM514260DTT-6
HM514260DTT-7
HM514260DTT-8
HM514260DLTT-6
HM514260DLTT-7
HM514260DLTT-8
HM51S4260DTT-6
HM51S4260DTT-7
HM51S4260DTT-8
HM51S4260DLTT-6
HM51S4260DLTT-7
HM51S4260DLTT-8
Access time
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
400-mill 44-pin plastic TSOP II (TTP-44/40DB)
Package
400-mill 40-pin plastic SOJ (CP-40D)
2
HM514260D, HM51S4260D Series
Pin Arrangement
HM514260DJ/DLJ Series
HM51S4260DJ/DLJ Series
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
HM514260DTT/DLTT Series
HM51S4260DTT/DLTT Series
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
V
CC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
(Top view)
(Top view)
Pin Description
Pin name
A0 to A8
Function
Address input
– Row address
– Column address
– Refresh address
Data-in/data-out
Row address strobe
Column address strobe
Read/write enable
Output enable
Power (+5 V)
Ground
No connection
A0 to A8
A0 to A8
A0 to A8
I/O0 to I/O15
RAS
UCAS, LCAS
WE
OE
V
CC
V
SS
NC
3
HM514260D, HM51S4260D Series
Block Diagram
I/O4
I/O4
buffer
I/O5
buffer
I/O6
buffer
I/O7
buffer
I/O3
I/O3
buffer
I/O2
I/O2
buffer
I/O1
I/O1
buffer
I/O0
I/O0
buffer
I/O15
I/O15
buffer
I/O14
I/O14
buffer
I/O13
I/O13
buffer
I/O12
I/O12
buffer
I/O11
buffer
I/O11
I/O5
I/O10
I/O10
buffer
I/O9
buffer
I/O8
buffer
I/O9
I/O6
I/O7
I/O8
Selector
Selector
Selector
Selector
I/O bus & column decoder
I/O bus & column decoder
I/O bus & column decoder
I/O bus & column decoder
256 k memory array Mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
Row
driver
Row Row
driver driver
Row
driver
Row
driver
Row Row
driver driver
Row
driver
256 k memory array mat
WE
RAS
UCAS
Row Decoder & Peripheral Circuit
LCAS
OE
Row
driver
Row Row
driver driver
Row
driver
Row
driver
Row Row
driver driver
Row
driver
I/O bus & column decoder
I/O bus & column decoder
I/O bus & column decoder
I/O bus & column decoder
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
Row address buffer
RA0 to RA8
Column address buffer
CA0 to CA8
Address A0 to A8
4
256 k memory array mat
HM514260D, HM51S4260D Series
Operation Mode
The HM51(S)4260D series has the following 11 operation modes.
1.
2.
3.
4.
5.
6.
7.
Read cycle
Early write cycle
Delayed write cycle
Read-modify-write cycle
RAS-only
refresh cycle
CAS-before-RAS
refresh cycle
Self refresh cycle(HM51S4260D)
8. Fast page mode read cycle
9. Fast page mode early write cycle
10. Fast page mode delayed write cycle
11. Fast page mode read-modify-write cycle
Inputs
RAS
H
H
L
L
L
L
L
H to L
LCAS
H
L
L
L
L
L
H
H
L
L
L
L
L
L
L
H to L
H to L
H to L
H to L
L
UCAS
H
L
L
L
L
L
H
L
H
L
H to L
H to L
H to L
H to L
L
H
L*
2
L*
2
H to L
H
L
D
H
L to H
H
Valid
Open
Undefined
Valid
Open
Fast page mode read cycle
Fast page mode early write cycle
Fast page mode delayed write cycle
Fast page mode read-modify-write cycle
Read cycle (Output disabled)
WE
D
H
H
L*
2
L*
2
H to L
D
D
OE
D
L
L
D
H
L to H
D
D
Output
Open
Valid
Valid
Open
Undefined
Valid
Open
Open
Operation
Standby
Standby
Read cycle
Early write cycle
Delayed write cycle
Read-modify-write cycle
RAS-only
refresh cycle
CAS-before-RAS
refresh cycle or
Self refresh cycle (HM51S4260D)
Notes: 1. H: High(inactive) L: Low(active) D: H or L
2. t
WCS
≥
0 ns
Early write cycle
t
WCS
< 0 ns
Delayed write cycle
3. Mode is determined by the OR function of the
UCAS
and
LCAS.
(Mode is set by the earliest of
UCAS
and
LCAS
active edge and reset by the latest of
UCAS
and
LCAS
inactive edge.) However
write OPERATION and output HIZ control are done independently by each
UCAS, LCAS.
ex. if
RAS
= H to L,
LCAS
= L,
UCAS
= H, then
CAS-before-RAS
refresh cycle is selected.
5
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