Final Datasheet
PE3282A
1.1 GHz/510 MHz
Dual Fractional-N
PLL IC for
Frequency Synthesis
Applications
• Cellular handsets
• Cellular base stations
• Spread-spectrum radio
• Cordless phones
• Pagers
Description
The PE3282A is a dual fractional-N phase-locked loop integrated circuit
designed for frequency synthesis and fabricated on Peregrine’s patented
UTSi® CMOS process. Each PLL includes a prescaler, phase detector, charge
pump and on-board fractional spur compensation. The 32/33 RF prescaler
(PLL1) operates up to 1.1 GHz and the
16/17 IF prescaler (PLL2) operates up to 510 MHz.
The PE3282A provides fractional-N division with power-of-two
denominator values up to 32. This allows comparison frequencies up to 32
times the channel spacing, providing a lower phase-noise floor than
integer PLLs.
Figure 1. PE3282A Block Diagram
f
in
1
f
in
1
Gnd
f
r
Gnd
6
5
7
8
9
Ref
Amp
9-Bit
Reference
Divider
21-Bit Serial Control
Interface
9-Bit
Reference
Divider
Gnd
f
in
2
f
in
2
14
16
15
16/17
Prescaler
18-Bit
Fractional-N
Main Divider
Fractional Spur
Compensation
Phase
Detector
Charge
Pump
32/33
Prescaler
19-Bit
Fractional-N
Main Divider
Features
• Modulo-32 fractional-N main counters
• On-board fractional spur compensation:
no tuning required, stable over
temperature
• Improved phase noise compared to
integer-N architectures
• Low power—8.5 mA at 3 V
• Integrated 1.1 GHz ÷ 32/33 prescaler
• Integrated 510 MHz ÷ 16/17 prescaler
Fractional Spur
Compensation
1
2
3
4
V
DD
V
DD
CP1
Gnd
f
o
LD
Gnd
CP2
V
DD
V
DD
Clock 11
Data
LE
12
13
Multiplexer
10
17
Phase
Detector
Charge
Pump
18
19
20
Peregrine Semiconductor Corporation
®
6175 Nancy Ridge Drive, San Diego, CA 92121
Tel (619) 455-0660 Fax (619) 455-0770
http://www.peregrine-semi.com
Document 70/0002~07B
PE3282A
Figure 2. Pin Configuration TSSOP (JEDEC MO-153-AC)
V
DD
V
DD
CP1
Gnd
f
in
1
f
in
1
Gnd
f
r
Gnd
f
o
LD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
V
DD
CP2
Gnd
f
in
2
f
in
2
Gnd
LE
Data
Clock
Table 1. PE3282A Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
V
DD
V
DD
Type
(Note 1)
(Note 1)
Output
Description
Power supply voltage input. Input may range from 2.7 V to 3.6 V. A bypass capacitor should be
placed as close as possible to this pin and be connected directly to the ground plane.
Same as pin 1.
Internal charge-pump output for PLL1. For connection to a loop filter for driving the input of
an external VCO.
Ground.
Prescaler input from the PLL1 (RF) VCO. 1.1 GHz max frequency.
1.1 GHz prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane. Capacitor is optional with
some loss of sensitivity.
Ground.
Reference frequency input.
Ground.
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect
signals, and data out of the shift register. CMOS output (see Table 10, f
o
LD Programming
Truth Table).
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the
21-bit shift register. A pull-down resistor is recommended.
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
A pull-down resistor is recommended.
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is
loaded into one of the four appropriate latches (as assigned by the control bits). A pull-down
resistor is recommended.
Ground.
510 MHz prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane. Capacitor is optional with
some loss of sensitivity.
Prescaler input from the PLL2 (IF) VCO. 510 MHz max frequency.
Ground.
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of
an external VCO.
Same as pin 1.
Same as pin 1.
CP1
Gnd
f
in
1
f
in
1
Gnd
f
r
Gnd
f
o
LD
Clock
Data
Input
Input
Input
Output
Input
Input
13
14
15
16
17
18
19
20
LE
Gnd
f
in
2
f
in
2
Gnd
CP2
V
DD
V
DD
Input
Input
Input
Output
(Note 1)
(Note 1)
Note 1: V
DD
pins 1, 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
2
Document 70/0002~07B
1.1 GHz/510 MHz Dual PLL IC
Ratings and Operating Ranges
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
T
stg
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input or output
Storage temperature range
Min
–0.3
–0.3
–10
–65
Max
4.0
V
DD
+ 0.3
+10
150
Unit
V
V
mA
°C
Table 3. Operating Ranges
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient temperature range
Min
2.7
–40
Max
3.6
85
Unit
V
°C
Table 4. ESD Ratings
Symbol
V
ESD
Parameter/Conditions
ESD Voltage, Human body model (Note 1)
Min
2000
Max
Unit
V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-STD-883, M3015 C2; 2KV.
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same precautions that you would use with other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-up Avoidance
Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up.
Document 70/0002~07B
Peregrine Semiconductor Corporation
®
3
PE3282A
Table 5. DC Characteristics
V
DD
= 3.0 V, –40° C < T
A
< 85° C, unless specified
Symbol
I
DD
Parameter
Operational supply current;
PLL1 (RF) enabled
PLL2 (IF) enabled
PLL1 and PLL2 enabled
Total standby current
Conditions
V
DD
= 2.7 to 3.6 V
5.5
3.0
8.5
25
mA
mA
mA
mA
Min
Typ
Max
Unit
I
stby
Digital inputs: Clock, Data, LE
V
IH
V
IL
I
IH
I
IL
High level input voltage
Low level input voltage
High level input current
Low level input current
V
DD
= 2.7 to 3.6 V
V
DD
= 2.7 to 3.6 V
V
IH
= V
DD
= 3.6 V
V
IL
= 0, V
DD
= 3.6 V
–1
–1
0.7 x V
DD
0.3 x V
DD
+1
+1
V
V
mA
mA
Reference Divider input: f
r
I
IHR
I
ILR
Input current
Input current
V
IH
= V
DD
= 3.6 V
V
IL
= 0, V
DD
= 3.6 V
–100
+100
mA
mA
Digital output: f
o
LD
V
OLD
V
OHD
Output voltage LOW
Output voltage HIGH
I
out
= 1 mA
I
out
= –1 mA
V
DD
– 0.4
0.4
V
V
Charge Pump outputs: CP1, CP2
I
CP - Source
I
CP - Sink
I
CPL
I
CP - Source
vs.
I
CP - Sink
I
CP
vs. T
A
Output current vs. temperature
I
CP
vs. V
CP
Output current magnitude variation vs.
voltage
Drive current
Leakage current
Sink vs. source mismatch
V
CP
= V
DD
/2, T
A
= 25° C
0.5 < V
CP
< V
DD
- 0.5 V
V
CP
= V
DD
/2, T
A
= 25° C
V
CP
= V
DD
/2 + 85° C
V
CP
= V
DD
/2 - 40° C
0.5 < V
CP
< V
DD
- 0.5 V,
T
A
= 25° C
–18
+8
20
–5
–70
70
5
20
mA
mA
nA
%
%
%
%
4
Document 70/0002~07B
1.1 GHz/510 MHz Dual PLL IC
Table 6. AC Characteristics
V
DD
= 3.0 V, –40° C < T
A
< 85° C, unless specified
Symbol
Parameter
Conditions
Min
Max
Unit
Serial Control Interface (see Figure 3)
f
Clock
t
ClockH
t
ClockL
t
DSU
t
DHLD
t
LEW
t
CLE
t
LEC
t
Data Out
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Data set-up time to Clock rising edge
Data hold time after Clock rising edge
LE pulse width
Clock falling edge to LE rising edge
LE falling edge to Clock rising edge
Data Out delay after Clock falling edge
(f
o
LD pin)
C
L
= 50 pf
50
50
50
10
50
50
50
90
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Main Divider (Including Prescaler)
f
in
1
f
in
2
P
fin
1
P
fin
2
f
c
Operating frequency
Operating frequency
Input level range
Input level range
Comparison frequency
External AC coupling
External AC coupling
100
45
–10
–10
1,100
510
5
5
10
MHz
MHz
dBm
dBm
MHz
Reference Divider
f
r
V
fr
Operating frequency
Input sensitivity
External AC coupling
(Note 1)
0.5
50
MHz
V
P-P
Note 1: CMOS logic levels may be used if DC coupled.
Document 70/0002~07B
Peregrine Semiconductor Corporation
®
5
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