MATRA MHS
HM 65799
64 K
×
4 with OE High Speed CMOS SRAM
Introduction
The HM 65799 is a high speed CMOS static RAM
organized as 65,536
×
4 bit. It is manufactured using MHS
high performance CMOS technology.
Access times as fast 20 ns are available with maximum
power consumption of only 770 mW.
The HM 65799 features fully static operation requiring no
external clocks or timing strobes. The automatic
power-down feature reduces the power consumption by
71 % when the circuit is deselected.
Easy memory expansion is provided by two active low
chip selects (CS1, CS2), an active low output enable (OE)
and three state drivers.
All inputs and outputs of the HM 65799 are TTL
compatible and operate from single 5 V supply thus
simplifying system design.
The HM 65799 is processed following the test methods of
MIL STD 883 and/or ESA/SCC 9000 making it ideally
suitable for military/space applications that demand
superior levels of performance and reliability.
Features
D
Fast access time
Commercial/industrial : 20/25/35/45/55 ns (max)
Military : 25/35/45/55 ns (max)
D
Low power consumption
Active : 770 mW
Standby : 220 mW
D
Wide temperature range : –55°C to + 125°C
D
D
D
D
300 mils width package
TTL compatible inputs and outputs
Asynchronous
Capable of withstanding greater than 2000V electrostatic
discharge
D
Output enable
D
Single 5 volt supply
Interface
Block Diagram
Rev. C (21/12/94)
1
HM 65799
Pin Configuration
Plastic 300 mils, 28 pins, DIL
Ceramic 300 mils, 28 pins, DIL
SO/SOJ 300 mils, 28 pins
MATRA MHS
Pinout DIL/SO 24 pins (top view)
Pin Names
A0–A15: Address inputs
I/00–I/03
CS1
CS2
: Input/Output
: Chip select 1
: Chip Select 2
OE
W
Vcc
GND
: Output enable
: Write enable
: Power
: Ground
Truth Table
CS1
H
X
L
L
L
CS2
X
H
L
L
L
W
X
X
H
L
H
OE
X
X
L
X
H
INPUT/
OUTPUTS
High Z
Data Out
Data In
High Z
MODE
Deselect/
Power Down
Read
Write
Deselected
L = Low, H = High, X = H or L, Z = High impedance.
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . –0.5 V to +7.0 V
DC input voltage : . . . . . . . . . . . . . . . . . . . . . . . . . . . –3.0 V to +7.0 V
DC output voltage in high Z state : . . . . . . . . . . . . . . –0.5 V to +7.0 V
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Electro Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . > 2000 V
(MIL STD 883C METHOD 3015-5)
Operating Range
OPERATING VOLTAGE
Military
Industrial
Commercial
(– 2)
(– 9)
(– 5)
5 V
±
10 %
5 V
±
10 %
5 V
±
10 %
OPERATING TEMPERATURE
– 55_C to + 125_C
– 40_C to + 85_C
– 0_C to + 70_C
Recommended DC Operating Conditions
PARAMETER
Vcc
Gnd
VIL
VIH
DESCRIPTION
Supply Voltage
Ground
Input low voltage
Input high voltage
MINIMUM
4.5
0.0
– 3.0
2.2
TYPICAL
5.0
0.0
0.0
–
MAXIMUM
5.5
0.0
0.8
VCC
UNIT
V
V
V
V
2
Rev. C (21/12/94)
MATRA MHS
Capacitance
PARAMETER
Cin
Cout
Note :
(1)
(1)
HM 65799
DESCRIPTION
Input capacitance
Output capacitance
MINIMUM
–
–
TYPICAL
–
–
MAXIMUM
5
7
UNIT
pF
pF
1. TA = 25°C, f = 1 MHz, Vcc = 5.0 V, these parameters are not tested.
AC Test Loads and Waveforms
(a)
(b)
Equivalent to : THEVENIN EQUIVALENT
DC Parameters
PARAMETER
IIX
IOZ
IOS
VOL
VOH
Note :
(2)
(3)
(4)
(5)
(2)
DESCRIPTION
Input leakage current
Output leakage current
Output short circuit current
Output low voltage
Output high voltage
MINIMUM
– 10.0
– 10.0
–
–
2.4
TYPICAL
–
–
–
–
–
MAXIMUM
10.0
10.0
– 350.0
0.4
–
UNIT
µA
µA
mA
V
V
2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled.
3. Vcc = max, Vout = Gnd, duration of the short circuit should not exceed 30 seconds.
Not more than 1 output should be shorted at one time.
4. Vcc min, IOL = 8.0 mA.
5. Vcc min, IOH = –4.0 mA.
Rev. C (21/12/94)
3
HM 65799
Consumption for Commercial (–5) Specification
SYMBOL
ICCSB
ICCSB1
ICCOP
(6)
(8)
(7)
MATRA MHS
PARAMETER
Standby supply current
Standby supply current
Dynamic operating current
65799
F–5
40
20
140
65799
H–5
35
20
120
65799
K–5
35
20
120
65799
M–5
35
20
120
65799
N–5
35
20
120
UNIT
mA
mA
mA
VALUE
max
max
max
Consumption for Industrial (–9) and Military (–2) Specification
SYMBOL
ICCSB
ICCSB1
ICCOP
Note :
(6)
(8)
(7)
PARAMETER
Standby supply current
Standby supply current
Dynamic operating current
65799
F–9
40
20
150
65799
H–9/–2
35
20
130
65799
K–9/–2
35
20
130
65799
M–9/–2
35
20
130
65799
N–9/–2
35
20
130
UNIT
mA
mA
mA
VALUE
max
max
max
6. CS
≥
VIH, a pull-up resistor to Vcc on the CS is required to keep the device unselected during the Vcc power-up. Otherwise
IccSB will exceed the above values. Min duty cycle = 100 %.
7. Vcc max, Output current = 0 mA, f = max, Vin = Vcc or Gnd.
8. CS
≥
Vcc – 0.3 V Iout = 0 mA.
AC Parameters
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V
Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output loading IOL/IOH
(see figure 1a and 1b)
: . . . . . . . . . . . +30 pF
Write Cycle : Commercial, Industrial and Military Specification
SYMBOL
TAVAV
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ(9)
TWLWH
TWHAX
TWHDX
TWHQX
Note :
(9)
PARAMETER
Write cycle time
Address set–up time
Address valid to write end
Data set–up time
CS1, CS2 low to write end
Write low to high Z
Write pulse width
Address hold from write end
Data hold time
Write high to low Z
65799
F–5/–9
20
0
15
10
15
10
15
0
0
3
65799
H–5/–9
/–2
20
0
20
15
20
13
20
0
0
3
65799
K–5/–9
/–2
30
0
25
17
30
15
25
0
0
3
65799
M–5/–9
/–2
40
0
35
20
40
20
30
0
0
3
65799
N–5/–9
/–2
50
0
40
25
50
25
35
0
0
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VALUE
min
min
min
min
min
max
min
min
min
min
9. The data input set-up and hold timing should be referenced to rising edge of the signal that terminates the write.
4
Rev. C (21/12/94)
MATRA MHS
Write Cycle 1 : W Controlled (note 10)
HM 65799
Write Cycle 2 : CS controlled (note 10)
Note :
10. The internal write of the memory is defined by the overlap of CS LOW and W LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to rising edge of the signal that
terminates the write.
Data out will be high impedance if OE = VIH.
Rev. C (21/12/94)
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
