HN58C256AI Series
32768-word
×
8-bit Electrically Erasable and Programmable
CMOS ROM
ADE-203-555C (Z)
Rev. 3.0
Sep. 5, 1997
Description
The Hitachi HN58C256AI is a electrically erasable and programmable ROM organized as 32768-word
×
8-
bit. It has realized high speed low power consumption and high reliability by employing advanced MNOS
memory technology and CMOS process and circuitry technology. They also have a 64-byte page
programming function to make their write operations faster.
Features
•
Single supply: 5 V
±
10%
•
Access time: 85/100 ns (max)
•
Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110
µW
(max)
•
On-chip latches: address, data,
CE, OE, WE
•
Automatic byte write: 10 ms max
•
Automatic page write (64 bytes): 10 ms max
•
Data
polling and Toggle bit
•
Data protection circuit on power on/off
•
Conforms to JEDEC byte-wide standard
•
Reliable CMOS with MNOS cell technology
•
10
5
erase/write cycles (in page mode)
•
10 years data retention
•
Software data protection
•
Wide temperature range: –40 to 85˚C
HN58C256AI Series
Ordering Information
Type No.
HN58C256AFPI-85
HN58C256AFPI-10
HN58C256ATI-85
HN58C256ATI-10
Access time
85 ns
100 ns
85 ns
100 ns
Package
400 mil 28-pin plastic SOP (FP-28D)
28-pin plastic TSOP (TFP-28DB)
Pin Arrangement
HN58C256AFPI Series
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(Top view)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
15
16
17
18
19
20
21
22
23
24
25
26
27
28
(Top view)
HN58C256ATI Series
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A4
A5
A6
A7
A12
A14
V
CC
WE
A13
A8
A9
A11
OE
Pin Description
Pin name
A0 to A14
I/O0 to I/O7
OE
CE
WE
V
CC
V
SS
Function
Address input
Data input/output
Output enable
Chip enable
Write enable
Power supply
Ground
2
HN58C256AI Series
Block Diagram
I/O0
High voltage generator
to
V
CC
V
SS
I/O7
OE
CE
WE
Control logic and timing
I/O buffer
and
input latch
A0
to
Y decoder
Y gating
A5
Address
buffer and
latch
A6
to
X decoder
Memory array
A14
Data latch
Operation Table
Operation
Read
Standby
Write
Deselect
Write inhibit
CE
V
IL
V
IH
V
IL
V
IL
×
×
Data polling
Program reset
Note:
1.
×
= Don’t care
V
IL
×
OE
V
IL
×*
1
V
IH
V
IH
×
V
IL
V
IL
×
WE
V
IH
×
V
IL
V
IH
V
IH
×
V
IH
×
I/O
Dout
High-Z
Din
High-Z
—
—
Dout (I/O7)
High-Z
3
HN58C256AI Series
Absolute Maximum Ratings
Parameter
Power supply voltage relative to V
SS
Input voltage relative to V
SS
Operating temperature range*
2
Storage temperature range
Symbol
V
CC
Vin
Topr
Tstg
Value
–0.6 to +7.0
–0.5*
1
to +7.0*
3
–40 to +85
–55 to +125
Unit
V
V
°C
°C
Notes: 1. Vin min = –3.0 V for pulse width
≤
50 ns
2. Including electrical characteristics and data retention
3. Should not exceed V
CC
+ 1.0 V.
Recommended DC Operating Conditions
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input voltage
V
IL
V
IH
Operating temperature
Topr
Notes: 1. V
IL
min: –1.0 V for pulse width
≤
50 ns.
2. V
IH
max: V
CC
+ 1.0 V for pulse width
≤
50 ns.
Min
4.5
0
–0.3*
1
3.0
–40
Typ
5.0
0
—
—
—
Max
5.5
0
0.6
Unit
V
V
V
°C
V
CC
+ 0.3*
2
V
85
DC Characteristics
Supply voltage range (V
CC
), temperature range (Topr) and input voltage (V
IH
/V
IL
) are referred to the table
of Recommended DC Operating Conditions.
Parameter
Input leakage current
Output leakage current
Standby V
CC
current
Symbol
I
LI
I
LO
I
CC1
I
CC2
Operating V
CC
current
I
CC3
Min
—
—
—
—
—
—
Output low voltage
Output high voltage
V
OL
V
OH
—
V
CC
×
0.8
Typ
—
—
—
—
—
—
—
—
Max
2
2
20
1
12
30
0.4
—
Unit
µA
µA
µA
mA
mA
mA
V
V
Test conditions
V
CC
= 5.5 V, Vin = 5.5 V
V
CC
= 5.5 V, Vout = 5.5/0.4 V
CE
= V
CC
CE
= V
IH
Iout = 0 mA, Duty = 100%,
Cycle = 1
µs
at V
CC
= 5.5 V
Iout = 0 mA, Duty = 100%,
Cycle = 85 ns at V
CC
= 5.5 V
I
OL
= 2.1 mA
I
OH
= –400
µA
4
HN58C256AI Series
Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Input capacitance*
1
Output capacitance*
1
Note:
Symbol
Cin
Cout
Min
—
—
Typ
—
—
Max
6
12
Unit
pF
pF
Test conditions
Vin = 0 V
Vout = 0 V
1. This parameter is periodically sampled and not 100% tested.
AC Characteristics
Supply voltage range (V
CC
), temperature range (Topr) are referred to the table of Recommended DC
Operating Conditions.
Test Conditions
•
Input pulse levels: 0 V to 3.0 V
•
•
•
•
Input rise and fall time:
≤
5 ns
Input timing reference levels: 0.8, 2.0 V
Output load: 1TTL Gate +100 pF
Output reference levels: 1.5 V, 1.5 V
Read Cycle
HN58C256AI
-85
Parameter
Address to output delay
CE
to output delay
OE
to output delay
Address to output hold
OE
(CE) high to output float*
1
Symbol
t
ACC
t
CE
t
OE
t
OH
t
DF
Min
—
—
10
0
0
Max
85
85
40
—
40
-10
Min
—
—
10
0
0
Max
100
100
50
—
40
Unit
ns
ns
ns
ns
ns
Test conditions
CE
=
OE
= V
IL
,
WE
= V
IH
OE
= V
IL
,
WE
= V
IH
CE
= V
IL
,
WE
= V
IH
CE
=
OE
= V
IL
,
WE
= V
IH
CE
= V
IL
,
WE
= V
IH
5
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